x86: Instruction decoder API
Add x86 instruction decoder to arch-specific libraries. This decoder
can decode x86 instructions used in kernel into prefix, opcode, modrm,
sib, displacement and immediates. This can also show the length of
instructions.
This version introduces instruction attributes for decoding
instructions.
The instruction attribute tables are generated from the opcode map file
(x86-opcode-map.txt) by the generator script(gen-insn-attr-x86.awk).
Currently, the opcode maps are based on opcode maps in Intel(R) 64 and
IA-32 Architectures Software Developers Manual Vol.2: Appendix.A,
and consist of below two types of opcode tables.
1-byte/2-bytes/3-bytes opcodes, which has 256 elements, are
written as below;
Table: table-name
Referrer: escaped-name
opcode: mnemonic|GrpXXX [operand1[,operand2...]] [(extra1)[,(extra2)...] [| 2nd-mnemonic ...]
(or)
opcode: escape # escaped-name
EndTable
Group opcodes, which has 8 elements, are written as below;
GrpTable: GrpXXX
reg: mnemonic [operand1[,operand2...]] [(extra1)[,(extra2)...] [| 2nd-mnemonic ...]
EndTable
These opcode maps include a few SSE and FP opcodes (for setup), because
those opcodes are used in the kernel.
Signed-off-by: Masami Hiramatsu <mhiramat@redhat.com>
Signed-off-by: Jim Keniston <jkenisto@us.ibm.com>
Acked-by: H. Peter Anvin <hpa@zytor.com>
Cc: Ananth N Mavinakayanahalli <ananth@in.ibm.com>
Cc: Avi Kivity <avi@redhat.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Christoph Hellwig <hch@infradead.org>
Cc: Frank Ch. Eigler <fche@redhat.com>
Cc: Ingo Molnar <mingo@elte.hu>
Cc: Jason Baron <jbaron@redhat.com>
Cc: K.Prasad <prasad@linux.vnet.ibm.com>
Cc: Lai Jiangshan <laijs@cn.fujitsu.com>
Cc: Li Zefan <lizf@cn.fujitsu.com>
Cc: Przemysław Pawełczyk <przemyslaw@pawelczyk.it>
Cc: Roland McGrath <roland@redhat.com>
Cc: Sam Ravnborg <sam@ravnborg.org>
Cc: Srikar Dronamraju <srikar@linux.vnet.ibm.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Tom Zanussi <tzanussi@gmail.com>
Cc: Vegard Nossum <vegard.nossum@gmail.com>
LKML-Reference: <20090813203413.31965.49709.stgit@localhost.localdomain>
Signed-off-by: Frederic Weisbecker <fweisbec@gmail.com>
2009-08-13 20:34:13 +00:00
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# x86 Opcode Maps
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#
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#<Opcode maps>
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# Table: table-name
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# Referrer: escaped-name
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# opcode: mnemonic|GrpXXX [operand1[,operand2...]] [(extra1)[,(extra2)...] [| 2nd-mnemonic ...]
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# (or)
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# opcode: escape # escaped-name
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# EndTable
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#
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#<group maps>
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# GrpTable: GrpXXX
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# reg: mnemonic [operand1[,operand2...]] [(extra1)[,(extra2)...] [| 2nd-mnemonic ...]
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# EndTable
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#
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Table: one byte opcode
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Referrer:
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# 0x00 - 0x0f
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00: ADD Eb,Gb
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01: ADD Ev,Gv
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02: ADD Gb,Eb
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03: ADD Gv,Ev
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04: ADD AL,Ib
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05: ADD rAX,Iz
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06: PUSH ES (i64)
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07: POP ES (i64)
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08: OR Eb,Gb
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09: OR Ev,Gv
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0a: OR Gb,Eb
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0b: OR Gv,Ev
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0c: OR AL,Ib
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0d: OR rAX,Iz
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0e: PUSH CS (i64)
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0f: escape # 2-byte escape
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# 0x10 - 0x1f
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10: ADC Eb,Gb
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11: ADC Ev,Gv
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12: ADC Gb,Eb
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13: ADC Gv,Ev
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14: ADC AL,Ib
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15: ADC rAX,Iz
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16: PUSH SS (i64)
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17: POP SS (i64)
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18: SBB Eb,Gb
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19: SBB Ev,Gv
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1a: SBB Gb,Eb
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1b: SBB Gv,Ev
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1c: SBB AL,Ib
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1d: SBB rAX,Iz
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1e: PUSH DS (i64)
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1f: POP DS (i64)
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# 0x20 - 0x2f
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20: AND Eb,Gb
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21: AND Ev,Gv
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22: AND Gb,Eb
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23: AND Gv,Ev
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24: AND AL,Ib
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25: AND rAx,Iz
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26: SEG=ES (Prefix)
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27: DAA (i64)
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28: SUB Eb,Gb
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29: SUB Ev,Gv
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2a: SUB Gb,Eb
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2b: SUB Gv,Ev
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2c: SUB AL,Ib
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2d: SUB rAX,Iz
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2e: SEG=CS (Prefix)
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2f: DAS (i64)
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# 0x30 - 0x3f
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30: XOR Eb,Gb
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31: XOR Ev,Gv
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32: XOR Gb,Eb
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33: XOR Gv,Ev
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34: XOR AL,Ib
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35: XOR rAX,Iz
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36: SEG=SS (Prefix)
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37: AAA (i64)
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38: CMP Eb,Gb
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39: CMP Ev,Gv
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3a: CMP Gb,Eb
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3b: CMP Gv,Ev
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3c: CMP AL,Ib
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3d: CMP rAX,Iz
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3e: SEG=DS (Prefix)
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3f: AAS (i64)
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# 0x40 - 0x4f
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40: INC eAX (i64) | REX (o64)
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41: INC eCX (i64) | REX.B (o64)
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42: INC eDX (i64) | REX.X (o64)
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43: INC eBX (i64) | REX.XB (o64)
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44: INC eSP (i64) | REX.R (o64)
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45: INC eBP (i64) | REX.RB (o64)
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46: INC eSI (i64) | REX.RX (o64)
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47: INC eDI (i64) | REX.RXB (o64)
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48: DEC eAX (i64) | REX.W (o64)
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49: DEC eCX (i64) | REX.WB (o64)
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4a: DEC eDX (i64) | REX.WX (o64)
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4b: DEC eBX (i64) | REX.WXB (o64)
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4c: DEC eSP (i64) | REX.WR (o64)
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4d: DEC eBP (i64) | REX.WRB (o64)
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4e: DEC eSI (i64) | REX.WRX (o64)
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4f: DEC eDI (i64) | REX.WRXB (o64)
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# 0x50 - 0x5f
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50: PUSH rAX/r8 (d64)
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51: PUSH rCX/r9 (d64)
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52: PUSH rDX/r10 (d64)
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53: PUSH rBX/r11 (d64)
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54: PUSH rSP/r12 (d64)
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55: PUSH rBP/r13 (d64)
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56: PUSH rSI/r14 (d64)
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57: PUSH rDI/r15 (d64)
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58: POP rAX/r8 (d64)
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59: POP rCX/r9 (d64)
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5a: POP rDX/r10 (d64)
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5b: POP rBX/r11 (d64)
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5c: POP rSP/r12 (d64)
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5d: POP rBP/r13 (d64)
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5e: POP rSI/r14 (d64)
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5f: POP rDI/r15 (d64)
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# 0x60 - 0x6f
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60: PUSHA/PUSHAD (i64)
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61: POPA/POPAD (i64)
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62: BOUND Gv,Ma (i64)
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63: ARPL Ew,Gw (i64) | MOVSXD Gv,Ev (o64)
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64: SEG=FS (Prefix)
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65: SEG=GS (Prefix)
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66: Operand-Size (Prefix)
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67: Address-Size (Prefix)
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68: PUSH Iz (d64)
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69: IMUL Gv,Ev,Iz
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6a: PUSH Ib (d64)
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6b: IMUL Gv,Ev,Ib
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6c: INS/INSB Yb,DX
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6d: INS/INSW/INSD Yz,DX
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6e: OUTS/OUTSB DX,Xb
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6f: OUTS/OUTSW/OUTSD DX,Xz
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# 0x70 - 0x7f
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70: JO Jb
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71: JNO Jb
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72: JB/JNAE/JC Jb
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73: JNB/JAE/JNC Jb
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74: JZ/JE Jb
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75: JNZ/JNE Jb
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76: JBE/JNA Jb
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77: JNBE/JA Jb
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78: JS Jb
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79: JNS Jb
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7a: JP/JPE Jb
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7b: JNP/JPO Jb
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7c: JL/JNGE Jb
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7d: JNL/JGE Jb
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7e: JLE/JNG Jb
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7f: JNLE/JG Jb
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# 0x80 - 0x8f
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80: Grp1 Eb,Ib (1A)
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81: Grp1 Ev,Iz (1A)
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82: Grp1 Eb,Ib (1A),(i64)
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83: Grp1 Ev,Ib (1A)
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84: TEST Eb,Gb
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85: TEST Ev,Gv
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86: XCHG Eb,Gb
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87: XCHG Ev,Gv
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88: MOV Eb,Gb
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89: MOV Ev,Gv
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8a: MOV Gb,Eb
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8b: MOV Gv,Ev
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8c: MOV Ev,Sw
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8d: LEA Gv,M
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8e: MOV Sw,Ew
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8f: Grp1A (1A) | POP Ev (d64)
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# 0x90 - 0x9f
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90: NOP | PAUSE (F3) | XCHG r8,rAX
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91: XCHG rCX/r9,rAX
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92: XCHG rDX/r10,rAX
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93: XCHG rBX/r11,rAX
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94: XCHG rSP/r12,rAX
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95: XCHG rBP/r13,rAX
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96: XCHG rSI/r14,rAX
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97: XCHG rDI/r15,rAX
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98: CBW/CWDE/CDQE
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99: CWD/CDQ/CQO
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9a: CALLF Ap (i64)
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9b: FWAIT/WAIT
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9c: PUSHF/D/Q Fv (d64)
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9d: POPF/D/Q Fv (d64)
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9e: SAHF
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9f: LAHF
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# 0xa0 - 0xaf
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a0: MOV AL,Ob
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a1: MOV rAX,Ov
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a2: MOV Ob,AL
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a3: MOV Ov,rAX
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a4: MOVS/B Xb,Yb
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a5: MOVS/W/D/Q Xv,Yv
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a6: CMPS/B Xb,Yb
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a7: CMPS/W/D Xv,Yv
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a8: TEST AL,Ib
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a9: TEST rAX,Iz
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aa: STOS/B Yb,AL
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ab: STOS/W/D/Q Yv,rAX
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ac: LODS/B AL,Xb
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ad: LODS/W/D/Q rAX,Xv
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ae: SCAS/B AL,Yb
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af: SCAS/W/D/Q rAX,Xv
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# 0xb0 - 0xbf
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b0: MOV AL/R8L,Ib
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b1: MOV CL/R9L,Ib
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b2: MOV DL/R10L,Ib
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b3: MOV BL/R11L,Ib
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b4: MOV AH/R12L,Ib
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b5: MOV CH/R13L,Ib
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b6: MOV DH/R14L,Ib
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b7: MOV BH/R15L,Ib
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b8: MOV rAX/r8,Iv
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b9: MOV rCX/r9,Iv
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ba: MOV rDX/r10,Iv
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bb: MOV rBX/r11,Iv
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bc: MOV rSP/r12,Iv
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bd: MOV rBP/r13,Iv
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be: MOV rSI/r14,Iv
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bf: MOV rDI/r15,Iv
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# 0xc0 - 0xcf
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c0: Grp2 Eb,Ib (1A)
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c1: Grp2 Ev,Ib (1A)
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c2: RETN Iw (f64)
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c3: RETN
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c4: LES Gz,Mp (i64)
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c5: LDS Gz,Mp (i64)
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c6: Grp11 Eb,Ib (1A)
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c7: Grp11 Ev,Iz (1A)
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c8: ENTER Iw,Ib
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c9: LEAVE (d64)
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ca: RETF Iw
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cb: RETF
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cc: INT3
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cd: INT Ib
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ce: INTO (i64)
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cf: IRET/D/Q
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# 0xd0 - 0xdf
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d0: Grp2 Eb,1 (1A)
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d1: Grp2 Ev,1 (1A)
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d2: Grp2 Eb,CL (1A)
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d3: Grp2 Ev,CL (1A)
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d4: AAM Ib (i64)
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d5: AAD Ib (i64)
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d6:
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d7: XLAT/XLATB
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d8: ESC
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d9: ESC
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da: ESC
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db: ESC
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dc: ESC
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dd: ESC
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de: ESC
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df: ESC
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# 0xe0 - 0xef
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e0: LOOPNE/LOOPNZ Jb (f64)
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e1: LOOPE/LOOPZ Jb (f64)
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e2: LOOP Jb (f64)
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e3: JrCXZ Jb (f64)
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e4: IN AL,Ib
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e5: IN eAX,Ib
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e6: OUT Ib,AL
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e7: OUT Ib,eAX
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e8: CALL Jz (f64)
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e9: JMP-near Jz (f64)
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|
|
|
ea: JMP-far Ap (i64)
|
|
|
|
|
eb: JMP-short Jb (f64)
|
|
|
|
|
ec: IN AL,DX
|
|
|
|
|
ed: IN eAX,DX
|
|
|
|
|
ee: OUT DX,AL
|
|
|
|
|
ef: OUT DX,eAX
|
|
|
|
|
# 0xf0 - 0xff
|
|
|
|
|
f0: LOCK (Prefix)
|
|
|
|
|
f1:
|
|
|
|
|
f2: REPNE (Prefix)
|
|
|
|
|
f3: REP/REPE (Prefix)
|
|
|
|
|
f4: HLT
|
|
|
|
|
f5: CMC
|
|
|
|
|
f6: Grp3_1 Eb (1A)
|
|
|
|
|
f7: Grp3_2 Ev (1A)
|
|
|
|
|
f8: CLC
|
|
|
|
|
f9: STC
|
|
|
|
|
fa: CLI
|
|
|
|
|
fb: STI
|
|
|
|
|
fc: CLD
|
|
|
|
|
fd: STD
|
|
|
|
|
fe: Grp4 (1A)
|
|
|
|
|
ff: Grp5 (1A)
|
|
|
|
|
EndTable
|
|
|
|
|
|
|
|
|
|
Table: 2-byte opcode # First Byte is 0x0f
|
|
|
|
|
Referrer: 2-byte escape
|
|
|
|
|
# 0x0f 0x00-0x0f
|
|
|
|
|
00: Grp6 (1A)
|
|
|
|
|
01: Grp7 (1A)
|
|
|
|
|
02: LAR Gv,Ew
|
|
|
|
|
03: LSL Gv,Ew
|
|
|
|
|
04:
|
|
|
|
|
05: SYSCALL (o64)
|
|
|
|
|
06: CLTS
|
|
|
|
|
07: SYSRET (o64)
|
|
|
|
|
08: INVD
|
|
|
|
|
09: WBINVD
|
|
|
|
|
0a:
|
|
|
|
|
0b: UD2 (1B)
|
|
|
|
|
0c:
|
|
|
|
|
0d: NOP Ev
|
|
|
|
|
0e:
|
|
|
|
|
0f:
|
|
|
|
|
# 0x0f 0x10-0x1f
|
2009-09-08 16:32:46 +00:00
|
|
|
10: movups Vps,Wps | movss Vss,Wss (F3) | movupd Vpd,Wpd (66) | movsd Vsd,Wsd (F2)
|
|
|
|
|
11: movups Wps,Vps | movss Wss,Vss (F3) | movupd Wpd,Vpd (66) | movsd Wsd,Vsd (F2)
|
|
|
|
|
12: movlps Vq,Mq | movlpd Vq,Mq (66) | movhlps Vq,Uq | movddup Vq,Wq (F2) | movsldup Vq,Wq (F3)
|
|
|
|
|
13: mpvlps Mq,Vq | movlpd Mq,Vq (66)
|
|
|
|
|
14: unpcklps Vps,Wq | unpcklpd Vpd,Wq (66)
|
|
|
|
|
15: unpckhps Vps,Wq | unpckhpd Vpd,Wq (66)
|
|
|
|
|
16: movhps Vq,Mq | movhpd Vq,Mq (66) | movlsps Vq,Uq | movshdup Vq,Wq (F3)
|
|
|
|
|
17: movhps Mq,Vq | movhpd Mq,Vq (66)
|
x86: Instruction decoder API
Add x86 instruction decoder to arch-specific libraries. This decoder
can decode x86 instructions used in kernel into prefix, opcode, modrm,
sib, displacement and immediates. This can also show the length of
instructions.
This version introduces instruction attributes for decoding
instructions.
The instruction attribute tables are generated from the opcode map file
(x86-opcode-map.txt) by the generator script(gen-insn-attr-x86.awk).
Currently, the opcode maps are based on opcode maps in Intel(R) 64 and
IA-32 Architectures Software Developers Manual Vol.2: Appendix.A,
and consist of below two types of opcode tables.
1-byte/2-bytes/3-bytes opcodes, which has 256 elements, are
written as below;
Table: table-name
Referrer: escaped-name
opcode: mnemonic|GrpXXX [operand1[,operand2...]] [(extra1)[,(extra2)...] [| 2nd-mnemonic ...]
(or)
opcode: escape # escaped-name
EndTable
Group opcodes, which has 8 elements, are written as below;
GrpTable: GrpXXX
reg: mnemonic [operand1[,operand2...]] [(extra1)[,(extra2)...] [| 2nd-mnemonic ...]
EndTable
These opcode maps include a few SSE and FP opcodes (for setup), because
those opcodes are used in the kernel.
Signed-off-by: Masami Hiramatsu <mhiramat@redhat.com>
Signed-off-by: Jim Keniston <jkenisto@us.ibm.com>
Acked-by: H. Peter Anvin <hpa@zytor.com>
Cc: Ananth N Mavinakayanahalli <ananth@in.ibm.com>
Cc: Avi Kivity <avi@redhat.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Christoph Hellwig <hch@infradead.org>
Cc: Frank Ch. Eigler <fche@redhat.com>
Cc: Ingo Molnar <mingo@elte.hu>
Cc: Jason Baron <jbaron@redhat.com>
Cc: K.Prasad <prasad@linux.vnet.ibm.com>
Cc: Lai Jiangshan <laijs@cn.fujitsu.com>
Cc: Li Zefan <lizf@cn.fujitsu.com>
Cc: Przemysław Pawełczyk <przemyslaw@pawelczyk.it>
Cc: Roland McGrath <roland@redhat.com>
Cc: Sam Ravnborg <sam@ravnborg.org>
Cc: Srikar Dronamraju <srikar@linux.vnet.ibm.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Tom Zanussi <tzanussi@gmail.com>
Cc: Vegard Nossum <vegard.nossum@gmail.com>
LKML-Reference: <20090813203413.31965.49709.stgit@localhost.localdomain>
Signed-off-by: Frederic Weisbecker <fweisbec@gmail.com>
2009-08-13 20:34:13 +00:00
|
|
|
18: Grp16 (1A)
|
|
|
|
|
19:
|
|
|
|
|
1a:
|
|
|
|
|
1b:
|
|
|
|
|
1c:
|
|
|
|
|
1d:
|
|
|
|
|
1e:
|
|
|
|
|
1f: NOP Ev
|
|
|
|
|
# 0x0f 0x20-0x2f
|
|
|
|
|
20: MOV Rd,Cd
|
|
|
|
|
21: MOV Rd,Dd
|
|
|
|
|
22: MOV Cd,Rd
|
|
|
|
|
23: MOV Dd,Rd
|
|
|
|
|
24:
|
|
|
|
|
25:
|
|
|
|
|
26:
|
|
|
|
|
27:
|
|
|
|
|
28: movaps Vps,Wps | movapd Vpd,Wpd (66)
|
|
|
|
|
29: movaps Wps,Vps | movapd Wpd,Vpd (66)
|
2009-09-08 16:32:46 +00:00
|
|
|
2a: cvtpi2ps Vps,Qpi | cvtsi2ss Vss,Ed/q (F3) | cvtpi2pd Vpd,Qpi (66) | cvtsi2sd Vsd,Ed/q (F2)
|
|
|
|
|
2b: movntps Mps,Vps | movntpd Mpd,Vpd (66)
|
|
|
|
|
2c: cvttps2pi Ppi,Wps | cvttss2si Gd/q,Wss (F3) | cvttpd2pi Ppi,Wpd (66) | cvttsd2si Gd/q,Wsd (F2)
|
|
|
|
|
2d: cvtps2pi Ppi,Wps | cvtss2si Gd/q,Wss (F3) | cvtpd2pi Qpi,Wpd (66) | cvtsd2si Gd/q,Wsd (F2)
|
|
|
|
|
2e: ucomiss Vss,Wss | ucomisd Vsd,Wsd (66)
|
|
|
|
|
2f: comiss Vss,Wss | comisd Vsd,Wsd (66)
|
x86: Instruction decoder API
Add x86 instruction decoder to arch-specific libraries. This decoder
can decode x86 instructions used in kernel into prefix, opcode, modrm,
sib, displacement and immediates. This can also show the length of
instructions.
This version introduces instruction attributes for decoding
instructions.
The instruction attribute tables are generated from the opcode map file
(x86-opcode-map.txt) by the generator script(gen-insn-attr-x86.awk).
Currently, the opcode maps are based on opcode maps in Intel(R) 64 and
IA-32 Architectures Software Developers Manual Vol.2: Appendix.A,
and consist of below two types of opcode tables.
1-byte/2-bytes/3-bytes opcodes, which has 256 elements, are
written as below;
Table: table-name
Referrer: escaped-name
opcode: mnemonic|GrpXXX [operand1[,operand2...]] [(extra1)[,(extra2)...] [| 2nd-mnemonic ...]
(or)
opcode: escape # escaped-name
EndTable
Group opcodes, which has 8 elements, are written as below;
GrpTable: GrpXXX
reg: mnemonic [operand1[,operand2...]] [(extra1)[,(extra2)...] [| 2nd-mnemonic ...]
EndTable
These opcode maps include a few SSE and FP opcodes (for setup), because
those opcodes are used in the kernel.
Signed-off-by: Masami Hiramatsu <mhiramat@redhat.com>
Signed-off-by: Jim Keniston <jkenisto@us.ibm.com>
Acked-by: H. Peter Anvin <hpa@zytor.com>
Cc: Ananth N Mavinakayanahalli <ananth@in.ibm.com>
Cc: Avi Kivity <avi@redhat.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Christoph Hellwig <hch@infradead.org>
Cc: Frank Ch. Eigler <fche@redhat.com>
Cc: Ingo Molnar <mingo@elte.hu>
Cc: Jason Baron <jbaron@redhat.com>
Cc: K.Prasad <prasad@linux.vnet.ibm.com>
Cc: Lai Jiangshan <laijs@cn.fujitsu.com>
Cc: Li Zefan <lizf@cn.fujitsu.com>
Cc: Przemysław Pawełczyk <przemyslaw@pawelczyk.it>
Cc: Roland McGrath <roland@redhat.com>
Cc: Sam Ravnborg <sam@ravnborg.org>
Cc: Srikar Dronamraju <srikar@linux.vnet.ibm.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Tom Zanussi <tzanussi@gmail.com>
Cc: Vegard Nossum <vegard.nossum@gmail.com>
LKML-Reference: <20090813203413.31965.49709.stgit@localhost.localdomain>
Signed-off-by: Frederic Weisbecker <fweisbec@gmail.com>
2009-08-13 20:34:13 +00:00
|
|
|
# 0x0f 0x30-0x3f
|
|
|
|
|
30: WRMSR
|
|
|
|
|
31: RDTSC
|
|
|
|
|
32: RDMSR
|
|
|
|
|
33: RDPMC
|
|
|
|
|
34: SYSENTER
|
|
|
|
|
35: SYSEXIT
|
|
|
|
|
36:
|
|
|
|
|
37: GETSEC
|
|
|
|
|
38: escape # 3-byte escape 1
|
|
|
|
|
39:
|
|
|
|
|
3a: escape # 3-byte escape 2
|
|
|
|
|
3b:
|
|
|
|
|
3c:
|
|
|
|
|
3d:
|
|
|
|
|
3e:
|
|
|
|
|
3f:
|
|
|
|
|
# 0x0f 0x40-0x4f
|
|
|
|
|
40: CMOVO Gv,Ev
|
|
|
|
|
41: CMOVNO Gv,Ev
|
|
|
|
|
42: CMOVB/C/NAE Gv,Ev
|
|
|
|
|
43: CMOVAE/NB/NC Gv,Ev
|
|
|
|
|
44: CMOVE/Z Gv,Ev
|
|
|
|
|
45: CMOVNE/NZ Gv,Ev
|
|
|
|
|
46: CMOVBE/NA Gv,Ev
|
|
|
|
|
47: CMOVA/NBE Gv,Ev
|
|
|
|
|
48: CMOVS Gv,Ev
|
|
|
|
|
49: CMOVNS Gv,Ev
|
|
|
|
|
4a: CMOVP/PE Gv,Ev
|
|
|
|
|
4b: CMOVNP/PO Gv,Ev
|
|
|
|
|
4c: CMOVL/NGE Gv,Ev
|
|
|
|
|
4d: CMOVNL/GE Gv,Ev
|
|
|
|
|
4e: CMOVLE/NG Gv,Ev
|
|
|
|
|
4f: CMOVNLE/G Gv,Ev
|
|
|
|
|
# 0x0f 0x50-0x5f
|
2009-09-08 16:32:46 +00:00
|
|
|
50: movmskps Gd/q,Ups | movmskpd Gd/q,Upd (66)
|
|
|
|
|
51: sqrtps Vps,Wps | sqrtss Vss,Wss (F3) | sqrtpd Vpd,Wpd (66) | sqrtsd Vsd,Wsd (F2)
|
|
|
|
|
52: rsqrtps Vps,Wps | rsqrtss Vss,Wss (F3)
|
|
|
|
|
53: rcpps Vps,Wps | rcpss Vss,Wss (F3)
|
|
|
|
|
54: andps Vps,Wps | andpd Vpd,Wpd (66)
|
|
|
|
|
55: andnps Vps,Wps | andnpd Vpd,Wpd (66)
|
|
|
|
|
56: orps Vps,Wps | orpd Vpd,Wpd (66)
|
|
|
|
|
57: xorps Vps,Wps | xorpd Vpd,Wpd (66)
|
|
|
|
|
58: addps Vps,Wps | addss Vss,Wss (F3) | addpd Vpd,Wpd (66) | addsd Vsd,Wsd (F2)
|
|
|
|
|
59: mulps Vps,Wps | mulss Vss,Wss (F3) | mulpd Vpd,Wpd (66) | mulsd Vsd,Wsd (F2)
|
|
|
|
|
5a: cvtps2pd Vpd,Wps | cvtss2sd Vsd,Wss (F3) | cvtpd2ps Vps,Wpd (66) | cvtsd2ss Vsd,Wsd (F2)
|
|
|
|
|
5b: cvtdq2ps Vps,Wdq | cvtps2dq Vdq,Wps (66) | cvttps2dq Vdq,Wps (F3)
|
|
|
|
|
5c: subps Vps,Wps | subss Vss,Wss (F3) | subpd Vpd,Wpd (66) | subsd Vsd,Wsd (F2)
|
|
|
|
|
5d: minps Vps,Wps | minss Vss,Wss (F3) | minpd Vpd,Wpd (66) | minsd Vsd,Wsd (F2)
|
|
|
|
|
5e: divps Vps,Wps | divss Vss,Wss (F3) | divpd Vpd,Wpd (66) | divsd Vsd,Wsd (F2)
|
|
|
|
|
5f: maxps Vps,Wps | maxss Vss,Wss (F3) | maxpd Vpd,Wpd (66) | maxsd Vsd,Wsd (F2)
|
x86: Instruction decoder API
Add x86 instruction decoder to arch-specific libraries. This decoder
can decode x86 instructions used in kernel into prefix, opcode, modrm,
sib, displacement and immediates. This can also show the length of
instructions.
This version introduces instruction attributes for decoding
instructions.
The instruction attribute tables are generated from the opcode map file
(x86-opcode-map.txt) by the generator script(gen-insn-attr-x86.awk).
Currently, the opcode maps are based on opcode maps in Intel(R) 64 and
IA-32 Architectures Software Developers Manual Vol.2: Appendix.A,
and consist of below two types of opcode tables.
1-byte/2-bytes/3-bytes opcodes, which has 256 elements, are
written as below;
Table: table-name
Referrer: escaped-name
opcode: mnemonic|GrpXXX [operand1[,operand2...]] [(extra1)[,(extra2)...] [| 2nd-mnemonic ...]
(or)
opcode: escape # escaped-name
EndTable
Group opcodes, which has 8 elements, are written as below;
GrpTable: GrpXXX
reg: mnemonic [operand1[,operand2...]] [(extra1)[,(extra2)...] [| 2nd-mnemonic ...]
EndTable
These opcode maps include a few SSE and FP opcodes (for setup), because
those opcodes are used in the kernel.
Signed-off-by: Masami Hiramatsu <mhiramat@redhat.com>
Signed-off-by: Jim Keniston <jkenisto@us.ibm.com>
Acked-by: H. Peter Anvin <hpa@zytor.com>
Cc: Ananth N Mavinakayanahalli <ananth@in.ibm.com>
Cc: Avi Kivity <avi@redhat.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Christoph Hellwig <hch@infradead.org>
Cc: Frank Ch. Eigler <fche@redhat.com>
Cc: Ingo Molnar <mingo@elte.hu>
Cc: Jason Baron <jbaron@redhat.com>
Cc: K.Prasad <prasad@linux.vnet.ibm.com>
Cc: Lai Jiangshan <laijs@cn.fujitsu.com>
Cc: Li Zefan <lizf@cn.fujitsu.com>
Cc: Przemysław Pawełczyk <przemyslaw@pawelczyk.it>
Cc: Roland McGrath <roland@redhat.com>
Cc: Sam Ravnborg <sam@ravnborg.org>
Cc: Srikar Dronamraju <srikar@linux.vnet.ibm.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Tom Zanussi <tzanussi@gmail.com>
Cc: Vegard Nossum <vegard.nossum@gmail.com>
LKML-Reference: <20090813203413.31965.49709.stgit@localhost.localdomain>
Signed-off-by: Frederic Weisbecker <fweisbec@gmail.com>
2009-08-13 20:34:13 +00:00
|
|
|
# 0x0f 0x60-0x6f
|
2009-09-08 16:32:46 +00:00
|
|
|
60: punpcklbw Pq,Qd | punpcklbw Vdq,Wdq (66)
|
|
|
|
|
61: punpcklwd Pq,Qd | punpcklwd Vdq,Wdq (66)
|
|
|
|
|
62: punpckldq Pq,Qd | punpckldq Vdq,Wdq (66)
|
|
|
|
|
63: packsswb Pq,Qq | packsswb Vdq,Wdq (66)
|
|
|
|
|
64: pcmpgtb Pq,Qq | pcmpgtb Vdq,Wdq (66)
|
|
|
|
|
65: pcmpgtw Pq,Qq | pcmpgtw(66) Vdq,Wdq
|
|
|
|
|
66: pcmpgtd Pq,Qq | pcmpgtd Vdq,Wdq (66)
|
|
|
|
|
67: packuswb Pq,Qq | packuswb(66) Vdq,Wdq
|
|
|
|
|
68: punpckhbw Pq,Qd | punpckhbw Vdq,Wdq (66)
|
|
|
|
|
69: punpckhwd Pq,Qd | punpckhwd Vdq,Wdq (66)
|
|
|
|
|
6a: punpckhdq Pq,Qd | punpckhdq Vdq,Wdq (66)
|
|
|
|
|
6b: packssdw Pq,Qd | packssdw Vdq,Wdq (66)
|
|
|
|
|
6c: punpcklqdq Vdq,Wdq (66)
|
|
|
|
|
6d: punpckhqdq Vdq,Wdq (66)
|
|
|
|
|
6e: movd/q/ Pd,Ed/q | movd/q Vdq,Ed/q (66)
|
|
|
|
|
6f: movq Pq,Qq | movdqa Vdq,Wdq (66) | movdqu Vdq,Wdq (F3)
|
x86: Instruction decoder API
Add x86 instruction decoder to arch-specific libraries. This decoder
can decode x86 instructions used in kernel into prefix, opcode, modrm,
sib, displacement and immediates. This can also show the length of
instructions.
This version introduces instruction attributes for decoding
instructions.
The instruction attribute tables are generated from the opcode map file
(x86-opcode-map.txt) by the generator script(gen-insn-attr-x86.awk).
Currently, the opcode maps are based on opcode maps in Intel(R) 64 and
IA-32 Architectures Software Developers Manual Vol.2: Appendix.A,
and consist of below two types of opcode tables.
1-byte/2-bytes/3-bytes opcodes, which has 256 elements, are
written as below;
Table: table-name
Referrer: escaped-name
opcode: mnemonic|GrpXXX [operand1[,operand2...]] [(extra1)[,(extra2)...] [| 2nd-mnemonic ...]
(or)
opcode: escape # escaped-name
EndTable
Group opcodes, which has 8 elements, are written as below;
GrpTable: GrpXXX
reg: mnemonic [operand1[,operand2...]] [(extra1)[,(extra2)...] [| 2nd-mnemonic ...]
EndTable
These opcode maps include a few SSE and FP opcodes (for setup), because
those opcodes are used in the kernel.
Signed-off-by: Masami Hiramatsu <mhiramat@redhat.com>
Signed-off-by: Jim Keniston <jkenisto@us.ibm.com>
Acked-by: H. Peter Anvin <hpa@zytor.com>
Cc: Ananth N Mavinakayanahalli <ananth@in.ibm.com>
Cc: Avi Kivity <avi@redhat.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Christoph Hellwig <hch@infradead.org>
Cc: Frank Ch. Eigler <fche@redhat.com>
Cc: Ingo Molnar <mingo@elte.hu>
Cc: Jason Baron <jbaron@redhat.com>
Cc: K.Prasad <prasad@linux.vnet.ibm.com>
Cc: Lai Jiangshan <laijs@cn.fujitsu.com>
Cc: Li Zefan <lizf@cn.fujitsu.com>
Cc: Przemysław Pawełczyk <przemyslaw@pawelczyk.it>
Cc: Roland McGrath <roland@redhat.com>
Cc: Sam Ravnborg <sam@ravnborg.org>
Cc: Srikar Dronamraju <srikar@linux.vnet.ibm.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Tom Zanussi <tzanussi@gmail.com>
Cc: Vegard Nossum <vegard.nossum@gmail.com>
LKML-Reference: <20090813203413.31965.49709.stgit@localhost.localdomain>
Signed-off-by: Frederic Weisbecker <fweisbec@gmail.com>
2009-08-13 20:34:13 +00:00
|
|
|
# 0x0f 0x70-0x7f
|
2009-09-08 16:32:46 +00:00
|
|
|
70: pshufw Pq,Qq,Ib | pshufd Vdq,Wdq,Ib (66) | pshufhw Vdq,Wdq,Ib (F3) | pshuflw VdqWdq,Ib (F2)
|
x86: Instruction decoder API
Add x86 instruction decoder to arch-specific libraries. This decoder
can decode x86 instructions used in kernel into prefix, opcode, modrm,
sib, displacement and immediates. This can also show the length of
instructions.
This version introduces instruction attributes for decoding
instructions.
The instruction attribute tables are generated from the opcode map file
(x86-opcode-map.txt) by the generator script(gen-insn-attr-x86.awk).
Currently, the opcode maps are based on opcode maps in Intel(R) 64 and
IA-32 Architectures Software Developers Manual Vol.2: Appendix.A,
and consist of below two types of opcode tables.
1-byte/2-bytes/3-bytes opcodes, which has 256 elements, are
written as below;
Table: table-name
Referrer: escaped-name
opcode: mnemonic|GrpXXX [operand1[,operand2...]] [(extra1)[,(extra2)...] [| 2nd-mnemonic ...]
(or)
opcode: escape # escaped-name
EndTable
Group opcodes, which has 8 elements, are written as below;
GrpTable: GrpXXX
reg: mnemonic [operand1[,operand2...]] [(extra1)[,(extra2)...] [| 2nd-mnemonic ...]
EndTable
These opcode maps include a few SSE and FP opcodes (for setup), because
those opcodes are used in the kernel.
Signed-off-by: Masami Hiramatsu <mhiramat@redhat.com>
Signed-off-by: Jim Keniston <jkenisto@us.ibm.com>
Acked-by: H. Peter Anvin <hpa@zytor.com>
Cc: Ananth N Mavinakayanahalli <ananth@in.ibm.com>
Cc: Avi Kivity <avi@redhat.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Christoph Hellwig <hch@infradead.org>
Cc: Frank Ch. Eigler <fche@redhat.com>
Cc: Ingo Molnar <mingo@elte.hu>
Cc: Jason Baron <jbaron@redhat.com>
Cc: K.Prasad <prasad@linux.vnet.ibm.com>
Cc: Lai Jiangshan <laijs@cn.fujitsu.com>
Cc: Li Zefan <lizf@cn.fujitsu.com>
Cc: Przemysław Pawełczyk <przemyslaw@pawelczyk.it>
Cc: Roland McGrath <roland@redhat.com>
Cc: Sam Ravnborg <sam@ravnborg.org>
Cc: Srikar Dronamraju <srikar@linux.vnet.ibm.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Tom Zanussi <tzanussi@gmail.com>
Cc: Vegard Nossum <vegard.nossum@gmail.com>
LKML-Reference: <20090813203413.31965.49709.stgit@localhost.localdomain>
Signed-off-by: Frederic Weisbecker <fweisbec@gmail.com>
2009-08-13 20:34:13 +00:00
|
|
|
71: Grp12 (1A)
|
|
|
|
|
72: Grp13 (1A)
|
|
|
|
|
73: Grp14 (1A)
|
2009-09-08 16:32:46 +00:00
|
|
|
74: pcmpeqb Pq,Qq | pcmpeqb Vdq,Wdq (66)
|
|
|
|
|
75: pcmpeqw Pq,Qq | pcmpeqw Vdq,Wdq (66)
|
|
|
|
|
76: pcmpeqd Pq,Qq | pcmpeqd Vdq,Wdq (66)
|
|
|
|
|
77: emms
|
x86: Instruction decoder API
Add x86 instruction decoder to arch-specific libraries. This decoder
can decode x86 instructions used in kernel into prefix, opcode, modrm,
sib, displacement and immediates. This can also show the length of
instructions.
This version introduces instruction attributes for decoding
instructions.
The instruction attribute tables are generated from the opcode map file
(x86-opcode-map.txt) by the generator script(gen-insn-attr-x86.awk).
Currently, the opcode maps are based on opcode maps in Intel(R) 64 and
IA-32 Architectures Software Developers Manual Vol.2: Appendix.A,
and consist of below two types of opcode tables.
1-byte/2-bytes/3-bytes opcodes, which has 256 elements, are
written as below;
Table: table-name
Referrer: escaped-name
opcode: mnemonic|GrpXXX [operand1[,operand2...]] [(extra1)[,(extra2)...] [| 2nd-mnemonic ...]
(or)
opcode: escape # escaped-name
EndTable
Group opcodes, which has 8 elements, are written as below;
GrpTable: GrpXXX
reg: mnemonic [operand1[,operand2...]] [(extra1)[,(extra2)...] [| 2nd-mnemonic ...]
EndTable
These opcode maps include a few SSE and FP opcodes (for setup), because
those opcodes are used in the kernel.
Signed-off-by: Masami Hiramatsu <mhiramat@redhat.com>
Signed-off-by: Jim Keniston <jkenisto@us.ibm.com>
Acked-by: H. Peter Anvin <hpa@zytor.com>
Cc: Ananth N Mavinakayanahalli <ananth@in.ibm.com>
Cc: Avi Kivity <avi@redhat.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Christoph Hellwig <hch@infradead.org>
Cc: Frank Ch. Eigler <fche@redhat.com>
Cc: Ingo Molnar <mingo@elte.hu>
Cc: Jason Baron <jbaron@redhat.com>
Cc: K.Prasad <prasad@linux.vnet.ibm.com>
Cc: Lai Jiangshan <laijs@cn.fujitsu.com>
Cc: Li Zefan <lizf@cn.fujitsu.com>
Cc: Przemysław Pawełczyk <przemyslaw@pawelczyk.it>
Cc: Roland McGrath <roland@redhat.com>
Cc: Sam Ravnborg <sam@ravnborg.org>
Cc: Srikar Dronamraju <srikar@linux.vnet.ibm.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Tom Zanussi <tzanussi@gmail.com>
Cc: Vegard Nossum <vegard.nossum@gmail.com>
LKML-Reference: <20090813203413.31965.49709.stgit@localhost.localdomain>
Signed-off-by: Frederic Weisbecker <fweisbec@gmail.com>
2009-08-13 20:34:13 +00:00
|
|
|
78: VMREAD Ed/q,Gd/q
|
|
|
|
|
79: VMWRITE Gd/q,Ed/q
|
|
|
|
|
7a:
|
|
|
|
|
7b:
|
2009-09-08 16:32:46 +00:00
|
|
|
7c: haddps(F2) Vps,Wps | haddpd(66) Vpd,Wpd
|
|
|
|
|
7d: hsubps(F2) Vps,Wps | hsubpd(66) Vpd,Wpd
|
|
|
|
|
7e: movd/q Ed/q,Pd | movd/q Ed/q,Vdq (66) | movq Vq,Wq (F3)
|
|
|
|
|
7f: movq Qq,Pq | movdqa Wdq,Vdq (66) | movdqu Wdq,Vdq (F3)
|
x86: Instruction decoder API
Add x86 instruction decoder to arch-specific libraries. This decoder
can decode x86 instructions used in kernel into prefix, opcode, modrm,
sib, displacement and immediates. This can also show the length of
instructions.
This version introduces instruction attributes for decoding
instructions.
The instruction attribute tables are generated from the opcode map file
(x86-opcode-map.txt) by the generator script(gen-insn-attr-x86.awk).
Currently, the opcode maps are based on opcode maps in Intel(R) 64 and
IA-32 Architectures Software Developers Manual Vol.2: Appendix.A,
and consist of below two types of opcode tables.
1-byte/2-bytes/3-bytes opcodes, which has 256 elements, are
written as below;
Table: table-name
Referrer: escaped-name
opcode: mnemonic|GrpXXX [operand1[,operand2...]] [(extra1)[,(extra2)...] [| 2nd-mnemonic ...]
(or)
opcode: escape # escaped-name
EndTable
Group opcodes, which has 8 elements, are written as below;
GrpTable: GrpXXX
reg: mnemonic [operand1[,operand2...]] [(extra1)[,(extra2)...] [| 2nd-mnemonic ...]
EndTable
These opcode maps include a few SSE and FP opcodes (for setup), because
those opcodes are used in the kernel.
Signed-off-by: Masami Hiramatsu <mhiramat@redhat.com>
Signed-off-by: Jim Keniston <jkenisto@us.ibm.com>
Acked-by: H. Peter Anvin <hpa@zytor.com>
Cc: Ananth N Mavinakayanahalli <ananth@in.ibm.com>
Cc: Avi Kivity <avi@redhat.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Christoph Hellwig <hch@infradead.org>
Cc: Frank Ch. Eigler <fche@redhat.com>
Cc: Ingo Molnar <mingo@elte.hu>
Cc: Jason Baron <jbaron@redhat.com>
Cc: K.Prasad <prasad@linux.vnet.ibm.com>
Cc: Lai Jiangshan <laijs@cn.fujitsu.com>
Cc: Li Zefan <lizf@cn.fujitsu.com>
Cc: Przemysław Pawełczyk <przemyslaw@pawelczyk.it>
Cc: Roland McGrath <roland@redhat.com>
Cc: Sam Ravnborg <sam@ravnborg.org>
Cc: Srikar Dronamraju <srikar@linux.vnet.ibm.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Tom Zanussi <tzanussi@gmail.com>
Cc: Vegard Nossum <vegard.nossum@gmail.com>
LKML-Reference: <20090813203413.31965.49709.stgit@localhost.localdomain>
Signed-off-by: Frederic Weisbecker <fweisbec@gmail.com>
2009-08-13 20:34:13 +00:00
|
|
|
# 0x0f 0x80-0x8f
|
|
|
|
|
80: JO Jz (f64)
|
|
|
|
|
81: JNO Jz (f64)
|
|
|
|
|
82: JB/JNAE/JC Jz (f64)
|
|
|
|
|
83: JNB/JAE/JNC Jz (f64)
|
|
|
|
|
84: JZ/JE Jz (f64)
|
|
|
|
|
85: JNZ/JNE Jz (f64)
|
|
|
|
|
86: JBE/JNA Jz (f64)
|
|
|
|
|
87: JNBE/JA Jz (f64)
|
|
|
|
|
88: JS Jz (f64)
|
|
|
|
|
89: JNS Jz (f64)
|
|
|
|
|
8a: JP/JPE Jz (f64)
|
|
|
|
|
8b: JNP/JPO Jz (f64)
|
|
|
|
|
8c: JL/JNGE Jz (f64)
|
|
|
|
|
8d: JNL/JGE Jz (f64)
|
|
|
|
|
8e: JLE/JNG Jz (f64)
|
|
|
|
|
8f: JNLE/JG Jz (f64)
|
|
|
|
|
# 0x0f 0x90-0x9f
|
|
|
|
|
90: SETO Eb
|
|
|
|
|
91: SETNO Eb
|
|
|
|
|
92: SETB/C/NAE Eb
|
|
|
|
|
93: SETAE/NB/NC Eb
|
|
|
|
|
94: SETE/Z Eb
|
|
|
|
|
95: SETNE/NZ Eb
|
|
|
|
|
96: SETBE/NA Eb
|
|
|
|
|
97: SETA/NBE Eb
|
|
|
|
|
98: SETS Eb
|
|
|
|
|
99: SETNS Eb
|
|
|
|
|
9a: SETP/PE Eb
|
|
|
|
|
9b: SETNP/PO Eb
|
|
|
|
|
9c: SETL/NGE Eb
|
|
|
|
|
9d: SETNL/GE Eb
|
|
|
|
|
9e: SETLE/NG Eb
|
|
|
|
|
9f: SETNLE/G Eb
|
|
|
|
|
# 0x0f 0xa0-0xaf
|
|
|
|
|
a0: PUSH FS (d64)
|
|
|
|
|
a1: POP FS (d64)
|
|
|
|
|
a2: CPUID
|
|
|
|
|
a3: BT Ev,Gv
|
|
|
|
|
a4: SHLD Ev,Gv,Ib
|
|
|
|
|
a5: SHLD Ev,Gv,CL
|
|
|
|
|
a6:
|
|
|
|
|
a7: GrpRNG
|
|
|
|
|
a8: PUSH GS (d64)
|
|
|
|
|
a9: POP GS (d64)
|
|
|
|
|
aa: RSM
|
|
|
|
|
ab: BTS Ev,Gv
|
|
|
|
|
ac: SHRD Ev,Gv,Ib
|
|
|
|
|
ad: SHRD Ev,Gv,CL
|
|
|
|
|
ae: Grp15 (1A),(1C)
|
|
|
|
|
af: IMUL Gv,Ev
|
|
|
|
|
# 0x0f 0xb0-0xbf
|
|
|
|
|
b0: CMPXCHG Eb,Gb
|
|
|
|
|
b1: CMPXCHG Ev,Gv
|
|
|
|
|
b2: LSS Gv,Mp
|
|
|
|
|
b3: BTR Ev,Gv
|
|
|
|
|
b4: LFS Gv,Mp
|
|
|
|
|
b5: LGS Gv,Mp
|
|
|
|
|
b6: MOVZX Gv,Eb
|
|
|
|
|
b7: MOVZX Gv,Ew
|
|
|
|
|
b8: JMPE | POPCNT Gv,Ev (F3)
|
|
|
|
|
b9: Grp10 (1A)
|
|
|
|
|
ba: Grp8 Ev,Ib (1A)
|
|
|
|
|
bb: BTC Ev,Gv
|
|
|
|
|
bc: BSF Gv,Ev
|
|
|
|
|
bd: BSR Gv,Ev
|
|
|
|
|
be: MOVSX Gv,Eb
|
|
|
|
|
bf: MOVSX Gv,Ew
|
|
|
|
|
# 0x0f 0xc0-0xcf
|
|
|
|
|
c0: XADD Eb,Gb
|
|
|
|
|
c1: XADD Ev,Gv
|
2009-09-08 16:32:46 +00:00
|
|
|
c2: cmpps Vps,Wps,Ib | cmpss Vss,Wss,Ib (F3) | cmppd Vpd,Wpd,Ib (66) | cmpsd Vsd,Wsd,Ib (F2)
|
x86: Instruction decoder API
Add x86 instruction decoder to arch-specific libraries. This decoder
can decode x86 instructions used in kernel into prefix, opcode, modrm,
sib, displacement and immediates. This can also show the length of
instructions.
This version introduces instruction attributes for decoding
instructions.
The instruction attribute tables are generated from the opcode map file
(x86-opcode-map.txt) by the generator script(gen-insn-attr-x86.awk).
Currently, the opcode maps are based on opcode maps in Intel(R) 64 and
IA-32 Architectures Software Developers Manual Vol.2: Appendix.A,
and consist of below two types of opcode tables.
1-byte/2-bytes/3-bytes opcodes, which has 256 elements, are
written as below;
Table: table-name
Referrer: escaped-name
opcode: mnemonic|GrpXXX [operand1[,operand2...]] [(extra1)[,(extra2)...] [| 2nd-mnemonic ...]
(or)
opcode: escape # escaped-name
EndTable
Group opcodes, which has 8 elements, are written as below;
GrpTable: GrpXXX
reg: mnemonic [operand1[,operand2...]] [(extra1)[,(extra2)...] [| 2nd-mnemonic ...]
EndTable
These opcode maps include a few SSE and FP opcodes (for setup), because
those opcodes are used in the kernel.
Signed-off-by: Masami Hiramatsu <mhiramat@redhat.com>
Signed-off-by: Jim Keniston <jkenisto@us.ibm.com>
Acked-by: H. Peter Anvin <hpa@zytor.com>
Cc: Ananth N Mavinakayanahalli <ananth@in.ibm.com>
Cc: Avi Kivity <avi@redhat.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Christoph Hellwig <hch@infradead.org>
Cc: Frank Ch. Eigler <fche@redhat.com>
Cc: Ingo Molnar <mingo@elte.hu>
Cc: Jason Baron <jbaron@redhat.com>
Cc: K.Prasad <prasad@linux.vnet.ibm.com>
Cc: Lai Jiangshan <laijs@cn.fujitsu.com>
Cc: Li Zefan <lizf@cn.fujitsu.com>
Cc: Przemysław Pawełczyk <przemyslaw@pawelczyk.it>
Cc: Roland McGrath <roland@redhat.com>
Cc: Sam Ravnborg <sam@ravnborg.org>
Cc: Srikar Dronamraju <srikar@linux.vnet.ibm.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Tom Zanussi <tzanussi@gmail.com>
Cc: Vegard Nossum <vegard.nossum@gmail.com>
LKML-Reference: <20090813203413.31965.49709.stgit@localhost.localdomain>
Signed-off-by: Frederic Weisbecker <fweisbec@gmail.com>
2009-08-13 20:34:13 +00:00
|
|
|
c3: movnti Md/q,Gd/q
|
2009-09-08 16:32:46 +00:00
|
|
|
c4: pinsrw Pq,Rd/q/Mw,Ib | pinsrw Vdq,Rd/q/Mw,Ib (66)
|
|
|
|
|
c5: pextrw Gd,Nq,Ib | pextrw Gd,Udq,Ib (66)
|
|
|
|
|
c6: shufps Vps,Wps,Ib | shufpd Vpd,Wpd,Ib (66)
|
x86: Instruction decoder API
Add x86 instruction decoder to arch-specific libraries. This decoder
can decode x86 instructions used in kernel into prefix, opcode, modrm,
sib, displacement and immediates. This can also show the length of
instructions.
This version introduces instruction attributes for decoding
instructions.
The instruction attribute tables are generated from the opcode map file
(x86-opcode-map.txt) by the generator script(gen-insn-attr-x86.awk).
Currently, the opcode maps are based on opcode maps in Intel(R) 64 and
IA-32 Architectures Software Developers Manual Vol.2: Appendix.A,
and consist of below two types of opcode tables.
1-byte/2-bytes/3-bytes opcodes, which has 256 elements, are
written as below;
Table: table-name
Referrer: escaped-name
opcode: mnemonic|GrpXXX [operand1[,operand2...]] [(extra1)[,(extra2)...] [| 2nd-mnemonic ...]
(or)
opcode: escape # escaped-name
EndTable
Group opcodes, which has 8 elements, are written as below;
GrpTable: GrpXXX
reg: mnemonic [operand1[,operand2...]] [(extra1)[,(extra2)...] [| 2nd-mnemonic ...]
EndTable
These opcode maps include a few SSE and FP opcodes (for setup), because
those opcodes are used in the kernel.
Signed-off-by: Masami Hiramatsu <mhiramat@redhat.com>
Signed-off-by: Jim Keniston <jkenisto@us.ibm.com>
Acked-by: H. Peter Anvin <hpa@zytor.com>
Cc: Ananth N Mavinakayanahalli <ananth@in.ibm.com>
Cc: Avi Kivity <avi@redhat.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Christoph Hellwig <hch@infradead.org>
Cc: Frank Ch. Eigler <fche@redhat.com>
Cc: Ingo Molnar <mingo@elte.hu>
Cc: Jason Baron <jbaron@redhat.com>
Cc: K.Prasad <prasad@linux.vnet.ibm.com>
Cc: Lai Jiangshan <laijs@cn.fujitsu.com>
Cc: Li Zefan <lizf@cn.fujitsu.com>
Cc: Przemysław Pawełczyk <przemyslaw@pawelczyk.it>
Cc: Roland McGrath <roland@redhat.com>
Cc: Sam Ravnborg <sam@ravnborg.org>
Cc: Srikar Dronamraju <srikar@linux.vnet.ibm.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Tom Zanussi <tzanussi@gmail.com>
Cc: Vegard Nossum <vegard.nossum@gmail.com>
LKML-Reference: <20090813203413.31965.49709.stgit@localhost.localdomain>
Signed-off-by: Frederic Weisbecker <fweisbec@gmail.com>
2009-08-13 20:34:13 +00:00
|
|
|
c7: Grp9 (1A)
|
|
|
|
|
c8: BSWAP RAX/EAX/R8/R8D
|
|
|
|
|
c9: BSWAP RCX/ECX/R9/R9D
|
|
|
|
|
ca: BSWAP RDX/EDX/R10/R10D
|
|
|
|
|
cb: BSWAP RBX/EBX/R11/R11D
|
|
|
|
|
cc: BSWAP RSP/ESP/R12/R12D
|
|
|
|
|
cd: BSWAP RBP/EBP/R13/R13D
|
|
|
|
|
ce: BSWAP RSI/ESI/R14/R14D
|
|
|
|
|
cf: BSWAP RDI/EDI/R15/R15D
|
|
|
|
|
# 0x0f 0xd0-0xdf
|
2009-09-08 16:32:46 +00:00
|
|
|
d0: addsubps Vps,Wps (F2) | addsubpd Vpd,Wpd (66)
|
|
|
|
|
d1: psrlw Pq,Qq | psrlw Vdq,Wdq (66)
|
|
|
|
|
d2: psrld Pq,Qq | psrld Vdq,Wdq (66)
|
|
|
|
|
d3: psrlq Pq,Qq | psrlq Vdq,Wdq (66)
|
|
|
|
|
d4: paddq Pq,Qq | paddq Vdq,Wdq (66)
|
|
|
|
|
d5: pmullw Pq,Qq | pmullw Vdq,Wdq (66)
|
|
|
|
|
d6: movq Wq,Vq (66) | movq2dq Vdq,Nq (F3) | movdq2q Pq,Uq (F2)
|
|
|
|
|
d7: pmovmskb Gd,Nq | pmovmskb Gd,Udq (66)
|
|
|
|
|
d8: psubusb Pq,Qq | psubusb Vdq,Wdq (66)
|
|
|
|
|
d9: psubusw Pq,Qq | psubusw Vdq,Wdq (66)
|
|
|
|
|
da: pminub Pq,Qq | pminub Vdq,Wdq (66)
|
|
|
|
|
db: pand Pq,Qq | pand Vdq,Wdq (66)
|
|
|
|
|
dc: paddusb Pq,Qq | paddusb Vdq,Wdq (66)
|
|
|
|
|
dd: paddusw Pq,Qq | paddusw Vdq,Wdq (66)
|
|
|
|
|
de: pmaxub Pq,Qq | pmaxub Vdq,Wdq (66)
|
|
|
|
|
df: pandn Pq,Qq | pandn Vdq,Wdq (66)
|
x86: Instruction decoder API
Add x86 instruction decoder to arch-specific libraries. This decoder
can decode x86 instructions used in kernel into prefix, opcode, modrm,
sib, displacement and immediates. This can also show the length of
instructions.
This version introduces instruction attributes for decoding
instructions.
The instruction attribute tables are generated from the opcode map file
(x86-opcode-map.txt) by the generator script(gen-insn-attr-x86.awk).
Currently, the opcode maps are based on opcode maps in Intel(R) 64 and
IA-32 Architectures Software Developers Manual Vol.2: Appendix.A,
and consist of below two types of opcode tables.
1-byte/2-bytes/3-bytes opcodes, which has 256 elements, are
written as below;
Table: table-name
Referrer: escaped-name
opcode: mnemonic|GrpXXX [operand1[,operand2...]] [(extra1)[,(extra2)...] [| 2nd-mnemonic ...]
(or)
opcode: escape # escaped-name
EndTable
Group opcodes, which has 8 elements, are written as below;
GrpTable: GrpXXX
reg: mnemonic [operand1[,operand2...]] [(extra1)[,(extra2)...] [| 2nd-mnemonic ...]
EndTable
These opcode maps include a few SSE and FP opcodes (for setup), because
those opcodes are used in the kernel.
Signed-off-by: Masami Hiramatsu <mhiramat@redhat.com>
Signed-off-by: Jim Keniston <jkenisto@us.ibm.com>
Acked-by: H. Peter Anvin <hpa@zytor.com>
Cc: Ananth N Mavinakayanahalli <ananth@in.ibm.com>
Cc: Avi Kivity <avi@redhat.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Christoph Hellwig <hch@infradead.org>
Cc: Frank Ch. Eigler <fche@redhat.com>
Cc: Ingo Molnar <mingo@elte.hu>
Cc: Jason Baron <jbaron@redhat.com>
Cc: K.Prasad <prasad@linux.vnet.ibm.com>
Cc: Lai Jiangshan <laijs@cn.fujitsu.com>
Cc: Li Zefan <lizf@cn.fujitsu.com>
Cc: Przemysław Pawełczyk <przemyslaw@pawelczyk.it>
Cc: Roland McGrath <roland@redhat.com>
Cc: Sam Ravnborg <sam@ravnborg.org>
Cc: Srikar Dronamraju <srikar@linux.vnet.ibm.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Tom Zanussi <tzanussi@gmail.com>
Cc: Vegard Nossum <vegard.nossum@gmail.com>
LKML-Reference: <20090813203413.31965.49709.stgit@localhost.localdomain>
Signed-off-by: Frederic Weisbecker <fweisbec@gmail.com>
2009-08-13 20:34:13 +00:00
|
|
|
# 0x0f 0xe0-0xef
|
2009-09-08 16:32:46 +00:00
|
|
|
e0: pavgb Pq,Qq | pavgb Vdq,Wdq (66)
|
|
|
|
|
e1: psraw Pq,Qq | psraw Vdq,Wdq (66)
|
|
|
|
|
e2: psrad Pq,Qq | psrad Vdq,Wdq (66)
|
|
|
|
|
e3: pavgw Pq,Qq | pavgw Vdq,Wdq (66)
|
|
|
|
|
e4: pmulhuw Pq,Qq | pmulhuw Vdq,Wdq (66)
|
|
|
|
|
e5: pmulhw Pq,Qq | pmulhw Vdq,Wdq (66)
|
|
|
|
|
e6: cvtpd2dq Vdq,Wpd (F2) | cvttpd2dq Vdq,Wpd (66) | cvtdq2pd Vpd,Wdq (F3)
|
|
|
|
|
e7: movntq Mq,Pq | movntdq Mdq,Vdq (66)
|
|
|
|
|
e8: psubsb Pq,Qq | psubsb Vdq,Wdq (66)
|
|
|
|
|
e9: psubsw Pq,Qq | psubsw Vdq,Wdq (66)
|
|
|
|
|
ea: pminsw Pq,Qq | pminsw Vdq,Wdq (66)
|
|
|
|
|
eb: por Pq,Qq | por Vdq,Wdq (66)
|
|
|
|
|
ec: paddsb Pq,Qq | paddsb Vdq,Wdq (66)
|
|
|
|
|
ed: paddsw Pq,Qq | paddsw Vdq,Wdq (66)
|
|
|
|
|
ee: pmaxsw Pq,Qq | pmaxsw Vdq,Wdq (66)
|
|
|
|
|
ef: pxor Pq,Qq | pxor Vdq,Wdq (66)
|
x86: Instruction decoder API
Add x86 instruction decoder to arch-specific libraries. This decoder
can decode x86 instructions used in kernel into prefix, opcode, modrm,
sib, displacement and immediates. This can also show the length of
instructions.
This version introduces instruction attributes for decoding
instructions.
The instruction attribute tables are generated from the opcode map file
(x86-opcode-map.txt) by the generator script(gen-insn-attr-x86.awk).
Currently, the opcode maps are based on opcode maps in Intel(R) 64 and
IA-32 Architectures Software Developers Manual Vol.2: Appendix.A,
and consist of below two types of opcode tables.
1-byte/2-bytes/3-bytes opcodes, which has 256 elements, are
written as below;
Table: table-name
Referrer: escaped-name
opcode: mnemonic|GrpXXX [operand1[,operand2...]] [(extra1)[,(extra2)...] [| 2nd-mnemonic ...]
(or)
opcode: escape # escaped-name
EndTable
Group opcodes, which has 8 elements, are written as below;
GrpTable: GrpXXX
reg: mnemonic [operand1[,operand2...]] [(extra1)[,(extra2)...] [| 2nd-mnemonic ...]
EndTable
These opcode maps include a few SSE and FP opcodes (for setup), because
those opcodes are used in the kernel.
Signed-off-by: Masami Hiramatsu <mhiramat@redhat.com>
Signed-off-by: Jim Keniston <jkenisto@us.ibm.com>
Acked-by: H. Peter Anvin <hpa@zytor.com>
Cc: Ananth N Mavinakayanahalli <ananth@in.ibm.com>
Cc: Avi Kivity <avi@redhat.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Christoph Hellwig <hch@infradead.org>
Cc: Frank Ch. Eigler <fche@redhat.com>
Cc: Ingo Molnar <mingo@elte.hu>
Cc: Jason Baron <jbaron@redhat.com>
Cc: K.Prasad <prasad@linux.vnet.ibm.com>
Cc: Lai Jiangshan <laijs@cn.fujitsu.com>
Cc: Li Zefan <lizf@cn.fujitsu.com>
Cc: Przemysław Pawełczyk <przemyslaw@pawelczyk.it>
Cc: Roland McGrath <roland@redhat.com>
Cc: Sam Ravnborg <sam@ravnborg.org>
Cc: Srikar Dronamraju <srikar@linux.vnet.ibm.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Tom Zanussi <tzanussi@gmail.com>
Cc: Vegard Nossum <vegard.nossum@gmail.com>
LKML-Reference: <20090813203413.31965.49709.stgit@localhost.localdomain>
Signed-off-by: Frederic Weisbecker <fweisbec@gmail.com>
2009-08-13 20:34:13 +00:00
|
|
|
# 0x0f 0xf0-0xff
|
2009-09-08 16:32:46 +00:00
|
|
|
f0: lddqu Vdq,Mdq (F2)
|
|
|
|
|
f1: psllw Pq,Qq | psllw Vdq,Wdq (66)
|
|
|
|
|
f2: pslld Pq,Qq | pslld Vdq,Wdq (66)
|
|
|
|
|
f3: psllq Pq,Qq | psllq Vdq,Wdq (66)
|
|
|
|
|
f4: pmuludq Pq,Qq | pmuludq Vdq,Wdq (66)
|
|
|
|
|
f5: pmaddwd Pq,Qq | pmaddwd Vdq,Wdq (66)
|
|
|
|
|
f6: psadbw Pq,Qq | psadbw Vdq,Wdq (66)
|
|
|
|
|
f7: maskmovq Pq,Nq | maskmovdqu Vdq,Udq (66)
|
|
|
|
|
f8: psubb Pq,Qq | psubb Vdq,Wdq (66)
|
|
|
|
|
f9: psubw Pq,Qq | psubw Vdq,Wdq (66)
|
|
|
|
|
fa: psubd Pq,Qq | psubd Vdq,Wdq (66)
|
|
|
|
|
fb: psubq Pq,Qq | psubq Vdq,Wdq (66)
|
|
|
|
|
fc: paddb Pq,Qq | paddb Vdq,Wdq (66)
|
|
|
|
|
fd: paddw Pq,Qq | paddw Vdq,Wdq (66)
|
|
|
|
|
fe: paddd Pq,Qq | paddd Vdq,Wdq (66)
|
x86: Instruction decoder API
Add x86 instruction decoder to arch-specific libraries. This decoder
can decode x86 instructions used in kernel into prefix, opcode, modrm,
sib, displacement and immediates. This can also show the length of
instructions.
This version introduces instruction attributes for decoding
instructions.
The instruction attribute tables are generated from the opcode map file
(x86-opcode-map.txt) by the generator script(gen-insn-attr-x86.awk).
Currently, the opcode maps are based on opcode maps in Intel(R) 64 and
IA-32 Architectures Software Developers Manual Vol.2: Appendix.A,
and consist of below two types of opcode tables.
1-byte/2-bytes/3-bytes opcodes, which has 256 elements, are
written as below;
Table: table-name
Referrer: escaped-name
opcode: mnemonic|GrpXXX [operand1[,operand2...]] [(extra1)[,(extra2)...] [| 2nd-mnemonic ...]
(or)
opcode: escape # escaped-name
EndTable
Group opcodes, which has 8 elements, are written as below;
GrpTable: GrpXXX
reg: mnemonic [operand1[,operand2...]] [(extra1)[,(extra2)...] [| 2nd-mnemonic ...]
EndTable
These opcode maps include a few SSE and FP opcodes (for setup), because
those opcodes are used in the kernel.
Signed-off-by: Masami Hiramatsu <mhiramat@redhat.com>
Signed-off-by: Jim Keniston <jkenisto@us.ibm.com>
Acked-by: H. Peter Anvin <hpa@zytor.com>
Cc: Ananth N Mavinakayanahalli <ananth@in.ibm.com>
Cc: Avi Kivity <avi@redhat.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Christoph Hellwig <hch@infradead.org>
Cc: Frank Ch. Eigler <fche@redhat.com>
Cc: Ingo Molnar <mingo@elte.hu>
Cc: Jason Baron <jbaron@redhat.com>
Cc: K.Prasad <prasad@linux.vnet.ibm.com>
Cc: Lai Jiangshan <laijs@cn.fujitsu.com>
Cc: Li Zefan <lizf@cn.fujitsu.com>
Cc: Przemysław Pawełczyk <przemyslaw@pawelczyk.it>
Cc: Roland McGrath <roland@redhat.com>
Cc: Sam Ravnborg <sam@ravnborg.org>
Cc: Srikar Dronamraju <srikar@linux.vnet.ibm.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Tom Zanussi <tzanussi@gmail.com>
Cc: Vegard Nossum <vegard.nossum@gmail.com>
LKML-Reference: <20090813203413.31965.49709.stgit@localhost.localdomain>
Signed-off-by: Frederic Weisbecker <fweisbec@gmail.com>
2009-08-13 20:34:13 +00:00
|
|
|
ff:
|
|
|
|
|
EndTable
|
|
|
|
|
|
|
|
|
|
Table: 3-byte opcode 1
|
|
|
|
|
Referrer: 3-byte escape 1
|
2009-09-08 16:32:46 +00:00
|
|
|
# 0x0f 0x38 0x00-0x0f
|
|
|
|
|
00: pshufb Pq,Qq | pshufb Vdq,Wdq (66)
|
|
|
|
|
01: phaddw Pq,Qq | phaddw Vdq,Wdq (66)
|
|
|
|
|
02: phaddd Pq,Qq | phaddd Vdq,Wdq (66)
|
|
|
|
|
03: phaddsw Pq,Qq | phaddsw Vdq,Wdq (66)
|
|
|
|
|
04: pmaddubsw Pq,Qq | pmaddubsw (66)Vdq,Wdq
|
|
|
|
|
05: phsubw Pq,Qq | phsubw Vdq,Wdq (66)
|
|
|
|
|
06: phsubd Pq,Qq | phsubd Vdq,Wdq (66)
|
|
|
|
|
07: phsubsw Pq,Qq | phsubsw Vdq,Wdq (66)
|
|
|
|
|
08: psignb Pq,Qq | psignb Vdq,Wdq (66)
|
|
|
|
|
09: psignw Pq,Qq | psignw Vdq,Wdq (66)
|
|
|
|
|
0a: psignd Pq,Qq | psignd Vdq,Wdq (66)
|
|
|
|
|
0b: pmulhrsw Pq,Qq | pmulhrsw Vdq,Wdq (66)
|
|
|
|
|
0c:
|
|
|
|
|
0d:
|
|
|
|
|
0e:
|
|
|
|
|
0f:
|
|
|
|
|
# 0x0f 0x38 0x10-0x1f
|
|
|
|
|
10: pblendvb Vdq,Wdq (66)
|
|
|
|
|
11:
|
|
|
|
|
12:
|
|
|
|
|
13:
|
|
|
|
|
14: blendvps Vdq,Wdq (66)
|
|
|
|
|
15: blendvpd Vdq,Wdq (66)
|
|
|
|
|
16:
|
|
|
|
|
17: ptest Vdq,Wdq (66)
|
|
|
|
|
18:
|
|
|
|
|
19:
|
|
|
|
|
1a:
|
|
|
|
|
1b:
|
|
|
|
|
1c: pabsb Pq,Qq | pabsb Vdq,Wdq (66)
|
|
|
|
|
1d: pabsw Pq,Qq | pabsw Vdq,Wdq (66)
|
|
|
|
|
1e: pabsd Pq,Qq | pabsd Vdq,Wdq (66)
|
|
|
|
|
1f:
|
|
|
|
|
# 0x0f 0x38 0x20-0x2f
|
|
|
|
|
20: pmovsxbw Vdq,Udq/Mq (66)
|
|
|
|
|
21: pmovsxbd Vdq,Udq/Md (66)
|
|
|
|
|
22: pmovsxbq Vdq,Udq/Mw (66)
|
|
|
|
|
23: pmovsxwd Vdq,Udq/Mq (66)
|
|
|
|
|
24: pmovsxwq Vdq,Udq/Md (66)
|
|
|
|
|
25: pmovsxdq Vdq,Udq/Mq (66)
|
|
|
|
|
26:
|
|
|
|
|
27:
|
|
|
|
|
28: pmuldq Vdq,Wdq (66)
|
|
|
|
|
29: pcmpeqq Vdq,Wdq (66)
|
|
|
|
|
2a: movntdqa Vdq,Mdq (66)
|
|
|
|
|
2b: packusdw Vdq,Wdq (66)
|
|
|
|
|
2c:
|
|
|
|
|
2d:
|
|
|
|
|
2e:
|
|
|
|
|
2f:
|
|
|
|
|
# 0x0f 0x38 0x30-0x3f
|
|
|
|
|
30: pmovzxbw Vdq,Udq/Mq (66)
|
|
|
|
|
31: pmovzxbd Vdq,Udq/Md (66)
|
|
|
|
|
32: pmovzxbq Vdq,Udq/Mw (66)
|
|
|
|
|
33: pmovzxwd Vdq,Udq/Mq (66)
|
|
|
|
|
34: pmovzxwq Vdq,Udq/Md (66)
|
|
|
|
|
35: pmovzxdq Vdq,Udq/Mq (66)
|
|
|
|
|
36:
|
|
|
|
|
37: pcmpgtq Vdq,Wdq (66)
|
|
|
|
|
38: pminsb Vdq,Wdq (66)
|
|
|
|
|
39: pminsd Vdq,Wdq (66)
|
|
|
|
|
3a: pminuw Vdq,Wdq (66)
|
|
|
|
|
3b: pminud Vdq,Wdq (66)
|
|
|
|
|
3c: pmaxsb Vdq,Wdq (66)
|
|
|
|
|
3d: pmaxsd Vdq,Wdq (66)
|
|
|
|
|
3e: pmaxuw Vdq,Wdq (66)
|
|
|
|
|
3f: pmaxud Vdq,Wdq (66)
|
|
|
|
|
# 0x0f 0x38 0x4f-0xff
|
|
|
|
|
40: pmulld Vdq,Wdq (66)
|
|
|
|
|
41: phminposuw Vdq,Wdq (66)
|
x86: Instruction decoder API
Add x86 instruction decoder to arch-specific libraries. This decoder
can decode x86 instructions used in kernel into prefix, opcode, modrm,
sib, displacement and immediates. This can also show the length of
instructions.
This version introduces instruction attributes for decoding
instructions.
The instruction attribute tables are generated from the opcode map file
(x86-opcode-map.txt) by the generator script(gen-insn-attr-x86.awk).
Currently, the opcode maps are based on opcode maps in Intel(R) 64 and
IA-32 Architectures Software Developers Manual Vol.2: Appendix.A,
and consist of below two types of opcode tables.
1-byte/2-bytes/3-bytes opcodes, which has 256 elements, are
written as below;
Table: table-name
Referrer: escaped-name
opcode: mnemonic|GrpXXX [operand1[,operand2...]] [(extra1)[,(extra2)...] [| 2nd-mnemonic ...]
(or)
opcode: escape # escaped-name
EndTable
Group opcodes, which has 8 elements, are written as below;
GrpTable: GrpXXX
reg: mnemonic [operand1[,operand2...]] [(extra1)[,(extra2)...] [| 2nd-mnemonic ...]
EndTable
These opcode maps include a few SSE and FP opcodes (for setup), because
those opcodes are used in the kernel.
Signed-off-by: Masami Hiramatsu <mhiramat@redhat.com>
Signed-off-by: Jim Keniston <jkenisto@us.ibm.com>
Acked-by: H. Peter Anvin <hpa@zytor.com>
Cc: Ananth N Mavinakayanahalli <ananth@in.ibm.com>
Cc: Avi Kivity <avi@redhat.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Christoph Hellwig <hch@infradead.org>
Cc: Frank Ch. Eigler <fche@redhat.com>
Cc: Ingo Molnar <mingo@elte.hu>
Cc: Jason Baron <jbaron@redhat.com>
Cc: K.Prasad <prasad@linux.vnet.ibm.com>
Cc: Lai Jiangshan <laijs@cn.fujitsu.com>
Cc: Li Zefan <lizf@cn.fujitsu.com>
Cc: Przemysław Pawełczyk <przemyslaw@pawelczyk.it>
Cc: Roland McGrath <roland@redhat.com>
Cc: Sam Ravnborg <sam@ravnborg.org>
Cc: Srikar Dronamraju <srikar@linux.vnet.ibm.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Tom Zanussi <tzanussi@gmail.com>
Cc: Vegard Nossum <vegard.nossum@gmail.com>
LKML-Reference: <20090813203413.31965.49709.stgit@localhost.localdomain>
Signed-off-by: Frederic Weisbecker <fweisbec@gmail.com>
2009-08-13 20:34:13 +00:00
|
|
|
80: INVEPT Gd/q,Mdq (66)
|
|
|
|
|
81: INVPID Gd/q,Mdq (66)
|
|
|
|
|
f0: MOVBE Gv,Mv | CRC32 Gd,Eb (F2)
|
|
|
|
|
f1: MOVBE Mv,Gv | CRC32 Gd,Ev (F2)
|
|
|
|
|
EndTable
|
|
|
|
|
|
|
|
|
|
Table: 3-byte opcode 2
|
|
|
|
|
Referrer: 3-byte escape 2
|
2009-09-08 16:32:46 +00:00
|
|
|
# 0x0f 0x3a 0x00-0xff
|
|
|
|
|
08: roundps Vdq,Wdq,Ib (66)
|
|
|
|
|
09: roundpd Vdq,Wdq,Ib (66)
|
|
|
|
|
0a: roundss Vss,Wss,Ib (66)
|
|
|
|
|
0b: roundsd Vsd,Wsd,Ib (66)
|
|
|
|
|
0c: blendps Vdq,Wdq,Ib (66)
|
|
|
|
|
0d: blendpd Vdq,Wdq,Ib (66)
|
|
|
|
|
0e: pblendw Vdq,Wdq,Ib (66)
|
|
|
|
|
0f: palignr Pq,Qq,Ib | palignr Vdq,Wdq,Ib (66)
|
|
|
|
|
14: pextrb Rd/Mb,Vdq,Ib (66)
|
|
|
|
|
15: pextrw Rd/Mw,Vdq,Ib (66)
|
|
|
|
|
16: pextrd/pextrq Ed/q,Vdq,Ib (66)
|
|
|
|
|
17: extractps Ed,Vdq,Ib (66)
|
|
|
|
|
20: pinsrb Vdq,Rd/q/Mb,Ib (66)
|
|
|
|
|
21: insertps Vdq,Udq/Md,Ib (66)
|
|
|
|
|
22: pinsrd/pinsrq Vdq,Ed/q,Ib (66)
|
|
|
|
|
40: dpps Vdq,Wdq,Ib (66)
|
|
|
|
|
41: dppd Vdq,Wdq,Ib (66)
|
|
|
|
|
42: mpsadbw Vdq,Wdq,Ib (66)
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60: pcmpestrm Vdq,Wdq,Ib (66)
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61: pcmpestri Vdq,Wdq,Ib (66)
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62: pcmpistrm Vdq,Wdq,Ib (66)
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63: pcmpistri Vdq,Wdq,Ib (66)
|
x86: Instruction decoder API
Add x86 instruction decoder to arch-specific libraries. This decoder
can decode x86 instructions used in kernel into prefix, opcode, modrm,
sib, displacement and immediates. This can also show the length of
instructions.
This version introduces instruction attributes for decoding
instructions.
The instruction attribute tables are generated from the opcode map file
(x86-opcode-map.txt) by the generator script(gen-insn-attr-x86.awk).
Currently, the opcode maps are based on opcode maps in Intel(R) 64 and
IA-32 Architectures Software Developers Manual Vol.2: Appendix.A,
and consist of below two types of opcode tables.
1-byte/2-bytes/3-bytes opcodes, which has 256 elements, are
written as below;
Table: table-name
Referrer: escaped-name
opcode: mnemonic|GrpXXX [operand1[,operand2...]] [(extra1)[,(extra2)...] [| 2nd-mnemonic ...]
(or)
opcode: escape # escaped-name
EndTable
Group opcodes, which has 8 elements, are written as below;
GrpTable: GrpXXX
reg: mnemonic [operand1[,operand2...]] [(extra1)[,(extra2)...] [| 2nd-mnemonic ...]
EndTable
These opcode maps include a few SSE and FP opcodes (for setup), because
those opcodes are used in the kernel.
Signed-off-by: Masami Hiramatsu <mhiramat@redhat.com>
Signed-off-by: Jim Keniston <jkenisto@us.ibm.com>
Acked-by: H. Peter Anvin <hpa@zytor.com>
Cc: Ananth N Mavinakayanahalli <ananth@in.ibm.com>
Cc: Avi Kivity <avi@redhat.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Christoph Hellwig <hch@infradead.org>
Cc: Frank Ch. Eigler <fche@redhat.com>
Cc: Ingo Molnar <mingo@elte.hu>
Cc: Jason Baron <jbaron@redhat.com>
Cc: K.Prasad <prasad@linux.vnet.ibm.com>
Cc: Lai Jiangshan <laijs@cn.fujitsu.com>
Cc: Li Zefan <lizf@cn.fujitsu.com>
Cc: Przemysław Pawełczyk <przemyslaw@pawelczyk.it>
Cc: Roland McGrath <roland@redhat.com>
Cc: Sam Ravnborg <sam@ravnborg.org>
Cc: Srikar Dronamraju <srikar@linux.vnet.ibm.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Tom Zanussi <tzanussi@gmail.com>
Cc: Vegard Nossum <vegard.nossum@gmail.com>
LKML-Reference: <20090813203413.31965.49709.stgit@localhost.localdomain>
Signed-off-by: Frederic Weisbecker <fweisbec@gmail.com>
2009-08-13 20:34:13 +00:00
|
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EndTable
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GrpTable: Grp1
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0: ADD
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1: OR
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2: ADC
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3: SBB
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4: AND
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5: SUB
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6: XOR
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7: CMP
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EndTable
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GrpTable: Grp1A
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0: POP
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EndTable
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GrpTable: Grp2
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0: ROL
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1: ROR
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2: RCL
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3: RCR
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4: SHL/SAL
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5: SHR
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6:
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7: SAR
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EndTable
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GrpTable: Grp3_1
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0: TEST Eb,Ib
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1:
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2: NOT Eb
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3: NEG Eb
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4: MUL AL,Eb
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5: IMUL AL,Eb
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6: DIV AL,Eb
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7: IDIV AL,Eb
|
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EndTable
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GrpTable: Grp3_2
|
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|
0: TEST Ev,Iz
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1:
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2: NOT Ev
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3: NEG Ev
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4: MUL rAX,Ev
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5: IMUL rAX,Ev
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6: DIV rAX,Ev
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7: IDIV rAX,Ev
|
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EndTable
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GrpTable: Grp4
|
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|
0: INC Eb
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1: DEC Eb
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EndTable
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GrpTable: Grp5
|
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0: INC Ev
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1: DEC Ev
|
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2: CALLN Ev (f64)
|
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3: CALLF Ep
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4: JMPN Ev (f64)
|
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5: JMPF Ep
|
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|
6: PUSH Ev (d64)
|
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7:
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EndTable
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GrpTable: Grp6
|
|
|
|
|
0: SLDT Rv/Mw
|
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|
|
1: STR Rv/Mw
|
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2: LLDT Ew
|
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3: LTR Ew
|
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4: VERR Ew
|
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5: VERW Ew
|
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|
EndTable
|
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|
GrpTable: Grp7
|
|
|
|
|
0: SGDT Ms | VMCALL (001),(11B) | VMLAUNCH (010),(11B) | VMRESUME (011),(11B) | VMXOFF (100),(11B)
|
|
|
|
|
1: SIDT Ms | MONITOR (000),(11B) | MWAIT (001)
|
|
|
|
|
2: LGDT Ms | XGETBV (000),(11B) | XSETBV (001),(11B)
|
|
|
|
|
3: LIDT Ms
|
|
|
|
|
4: SMSW Mw/Rv
|
|
|
|
|
5:
|
|
|
|
|
6: LMSW Ew
|
|
|
|
|
7: INVLPG Mb | SWAPGS (o64),(000),(11B) | RDTSCP (001),(11B)
|
|
|
|
|
EndTable
|
|
|
|
|
|
|
|
|
|
GrpTable: Grp8
|
|
|
|
|
4: BT
|
|
|
|
|
5: BTS
|
|
|
|
|
6: BTR
|
|
|
|
|
7: BTC
|
|
|
|
|
EndTable
|
|
|
|
|
|
|
|
|
|
GrpTable: Grp9
|
|
|
|
|
1: CMPXCHG8B/16B Mq/Mdq
|
|
|
|
|
6: VMPTRLD Mq | VMCLEAR Mq (66) | VMXON Mq (F3)
|
|
|
|
|
7: VMPTRST Mq
|
|
|
|
|
EndTable
|
|
|
|
|
|
|
|
|
|
GrpTable: Grp10
|
|
|
|
|
EndTable
|
|
|
|
|
|
|
|
|
|
GrpTable: Grp11
|
|
|
|
|
0: MOV
|
|
|
|
|
EndTable
|
|
|
|
|
|
|
|
|
|
GrpTable: Grp12
|
|
|
|
|
EndTable
|
|
|
|
|
|
|
|
|
|
GrpTable: Grp13
|
|
|
|
|
EndTable
|
|
|
|
|
|
|
|
|
|
GrpTable: Grp14
|
|
|
|
|
EndTable
|
|
|
|
|
|
|
|
|
|
GrpTable: Grp15
|
|
|
|
|
0: fxsave
|
|
|
|
|
1: fxstor
|
|
|
|
|
2: ldmxcsr
|
|
|
|
|
3: stmxcsr
|
|
|
|
|
4: XSAVE
|
|
|
|
|
5: XRSTOR | lfence (11B)
|
|
|
|
|
6: mfence (11B)
|
|
|
|
|
7: clflush | sfence (11B)
|
|
|
|
|
EndTable
|
|
|
|
|
|
|
|
|
|
GrpTable: Grp16
|
|
|
|
|
0: prefetch NTA
|
|
|
|
|
1: prefetch T0
|
|
|
|
|
2: prefetch T1
|
|
|
|
|
3: prefetch T2
|
|
|
|
|
EndTable
|
|
|
|
|
|
|
|
|
|
GrpTable: GrpRNG
|
|
|
|
|
0: xstore-rng
|
|
|
|
|
1: xcrypt-ecb
|
|
|
|
|
2: xcrypt-cbc
|
|
|
|
|
4: xcrypt-cfb
|
|
|
|
|
5: xcrypt-ofb
|
|
|
|
|
EndTable
|