2005-09-26 06:04:21 +00:00
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/*
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* Derived from "arch/i386/kernel/process.c"
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* Copyright (C) 1995 Linus Torvalds
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*
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* Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
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* Paul Mackerras (paulus@cs.anu.edu.au)
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*
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* PowerPC version
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/errno.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/smp.h>
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#include <linux/stddef.h>
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#include <linux/unistd.h>
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#include <linux/ptrace.h>
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#include <linux/slab.h>
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#include <linux/user.h>
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#include <linux/elf.h>
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#include <linux/init.h>
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#include <linux/prctl.h>
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#include <linux/init_task.h>
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2011-07-22 22:24:23 +00:00
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#include <linux/export.h>
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2005-09-26 06:04:21 +00:00
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#include <linux/kallsyms.h>
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#include <linux/mqueue.h>
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#include <linux/hardirq.h>
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2005-10-10 12:29:05 +00:00
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#include <linux/utsname.h>
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2009-02-10 05:10:27 +00:00
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#include <linux/ftrace.h>
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2008-12-31 14:11:38 +00:00
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#include <linux/kernel_stat.h>
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2009-02-22 01:50:03 +00:00
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#include <linux/personality.h>
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#include <linux/random.h>
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2010-06-15 06:05:19 +00:00
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#include <linux/hw_breakpoint.h>
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2005-09-26 06:04:21 +00:00
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#include <asm/pgtable.h>
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#include <asm/uaccess.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <asm/prom.h>
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2005-11-07 02:12:03 +00:00
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#include <asm/machdep.h>
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powerpc: Implement accurate task and CPU time accounting
This implements accurate task and cpu time accounting for 64-bit
powerpc kernels. Instead of accounting a whole jiffy of time to a
task on a timer interrupt because that task happened to be running at
the time, we now account time in units of timebase ticks according to
the actual time spent by the task in user mode and kernel mode. We
also count the time spent processing hardware and software interrupts
accurately. This is conditional on CONFIG_VIRT_CPU_ACCOUNTING. If
that is not set, we do tick-based approximate accounting as before.
To get this accurate information, we read either the PURR (processor
utilization of resources register) on POWER5 machines, or the timebase
on other machines on
* each entry to the kernel from usermode
* each exit to usermode
* transitions between process context, hard irq context and soft irq
context in kernel mode
* context switches.
On POWER5 systems with shared-processor logical partitioning we also
read both the PURR and the timebase at each timer interrupt and
context switch in order to determine how much time has been taken by
the hypervisor to run other partitions ("steal" time). Unfortunately,
since we need values of the PURR on both threads at the same time to
accurately calculate the steal time, and since we can only calculate
steal time on a per-core basis, the apportioning of the steal time
between idle time (time which we ceded to the hypervisor in the idle
loop) and actual stolen time is somewhat approximate at the moment.
This is all based quite heavily on what s390 does, and it uses the
generic interfaces that were added by the s390 developers,
i.e. account_system_time(), account_user_time(), etc.
This patch doesn't add any new interfaces between the kernel and
userspace, and doesn't change the units in which time is reported to
userspace by things such as /proc/stat, /proc/<pid>/stat, getrusage(),
times(), etc. Internally the various task and cpu times are stored in
timebase units, but they are converted to USER_HZ units (1/100th of a
second) when reported to userspace. Some precision is therefore lost
but there should not be any accumulating error, since the internal
accumulation is at full precision.
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-02-23 23:06:59 +00:00
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#include <asm/time.h>
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2012-03-28 17:30:02 +00:00
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#include <asm/runlatch.h>
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2006-03-22 23:00:08 +00:00
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#include <asm/syscalls.h>
|
2012-03-28 17:30:02 +00:00
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#include <asm/switch_to.h>
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#include <asm/debug.h>
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2005-10-10 12:29:05 +00:00
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#ifdef CONFIG_PPC64
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#include <asm/firmware.h>
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#endif
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2008-07-23 16:10:41 +00:00
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#include <linux/kprobes.h>
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#include <linux/kdebug.h>
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2005-09-26 06:04:21 +00:00
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extern unsigned long _get_SP(void);
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#ifndef CONFIG_SMP
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struct task_struct *last_task_used_math = NULL;
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struct task_struct *last_task_used_altivec = NULL;
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2008-06-25 04:07:18 +00:00
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struct task_struct *last_task_used_vsx = NULL;
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2005-09-26 06:04:21 +00:00
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struct task_struct *last_task_used_spe = NULL;
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#endif
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/*
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* Make sure the floating-point register state in the
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* the thread_struct is up to date for task tsk.
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*/
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void flush_fp_to_thread(struct task_struct *tsk)
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{
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if (tsk->thread.regs) {
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/*
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* We need to disable preemption here because if we didn't,
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* another process could get scheduled after the regs->msr
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* test but before we have finished saving the FP registers
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* to the thread_struct. That process could take over the
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* FPU, and then when we get scheduled again we would store
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* bogus values for the remaining FP registers.
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*/
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preempt_disable();
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if (tsk->thread.regs->msr & MSR_FP) {
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#ifdef CONFIG_SMP
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/*
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* This should only ever be called for current or
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* for a stopped child process. Since we save away
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* the FP register state on context switch on SMP,
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* there is something wrong if a stopped child appears
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* to still have its FP state in the CPU registers.
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*/
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BUG_ON(tsk != current);
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#endif
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2007-08-29 02:15:53 +00:00
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giveup_fpu(tsk);
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2005-09-26 06:04:21 +00:00
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}
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preempt_enable();
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}
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}
|
KVM: PPC: Add support for Book3S processors in hypervisor mode
This adds support for KVM running on 64-bit Book 3S processors,
specifically POWER7, in hypervisor mode. Using hypervisor mode means
that the guest can use the processor's supervisor mode. That means
that the guest can execute privileged instructions and access privileged
registers itself without trapping to the host. This gives excellent
performance, but does mean that KVM cannot emulate a processor
architecture other than the one that the hardware implements.
This code assumes that the guest is running paravirtualized using the
PAPR (Power Architecture Platform Requirements) interface, which is the
interface that IBM's PowerVM hypervisor uses. That means that existing
Linux distributions that run on IBM pSeries machines will also run
under KVM without modification. In order to communicate the PAPR
hypercalls to qemu, this adds a new KVM_EXIT_PAPR_HCALL exit code
to include/linux/kvm.h.
Currently the choice between book3s_hv support and book3s_pr support
(i.e. the existing code, which runs the guest in user mode) has to be
made at kernel configuration time, so a given kernel binary can only
do one or the other.
This new book3s_hv code doesn't support MMIO emulation at present.
Since we are running paravirtualized guests, this isn't a serious
restriction.
With the guest running in supervisor mode, most exceptions go straight
to the guest. We will never get data or instruction storage or segment
interrupts, alignment interrupts, decrementer interrupts, program
interrupts, single-step interrupts, etc., coming to the hypervisor from
the guest. Therefore this introduces a new KVMTEST_NONHV macro for the
exception entry path so that we don't have to do the KVM test on entry
to those exception handlers.
We do however get hypervisor decrementer, hypervisor data storage,
hypervisor instruction storage, and hypervisor emulation assist
interrupts, so we have to handle those.
In hypervisor mode, real-mode accesses can access all of RAM, not just
a limited amount. Therefore we put all the guest state in the vcpu.arch
and use the shadow_vcpu in the PACA only for temporary scratch space.
We allocate the vcpu with kzalloc rather than vzalloc, and we don't use
anything in the kvmppc_vcpu_book3s struct, so we don't allocate it.
We don't have a shared page with the guest, but we still need a
kvm_vcpu_arch_shared struct to store the values of various registers,
so we include one in the vcpu_arch struct.
The POWER7 processor has a restriction that all threads in a core have
to be in the same partition. MMU-on kernel code counts as a partition
(partition 0), so we have to do a partition switch on every entry to and
exit from the guest. At present we require the host and guest to run
in single-thread mode because of this hardware restriction.
This code allocates a hashed page table for the guest and initializes
it with HPTEs for the guest's Virtual Real Memory Area (VRMA). We
require that the guest memory is allocated using 16MB huge pages, in
order to simplify the low-level memory management. This also means that
we can get away without tracking paging activity in the host for now,
since huge pages can't be paged or swapped.
This also adds a few new exports needed by the book3s_hv code.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-06-29 00:21:34 +00:00
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|
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EXPORT_SYMBOL_GPL(flush_fp_to_thread);
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2005-09-26 06:04:21 +00:00
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void enable_kernel_fp(void)
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{
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WARN_ON(preemptible());
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#ifdef CONFIG_SMP
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if (current->thread.regs && (current->thread.regs->msr & MSR_FP))
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giveup_fpu(current);
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else
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giveup_fpu(NULL); /* just enables FP for kernel */
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#else
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giveup_fpu(last_task_used_math);
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#endif /* CONFIG_SMP */
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}
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EXPORT_SYMBOL(enable_kernel_fp);
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#ifdef CONFIG_ALTIVEC
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void enable_kernel_altivec(void)
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{
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WARN_ON(preemptible());
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#ifdef CONFIG_SMP
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if (current->thread.regs && (current->thread.regs->msr & MSR_VEC))
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giveup_altivec(current);
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else
|
2012-04-15 20:56:45 +00:00
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giveup_altivec_notask();
|
2005-09-26 06:04:21 +00:00
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#else
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giveup_altivec(last_task_used_altivec);
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#endif /* CONFIG_SMP */
|
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|
}
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EXPORT_SYMBOL(enable_kernel_altivec);
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|
|
/*
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|
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|
* Make sure the VMX/Altivec register state in the
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|
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|
* the thread_struct is up to date for task tsk.
|
|
|
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|
*/
|
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|
|
void flush_altivec_to_thread(struct task_struct *tsk)
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|
{
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|
|
|
|
if (tsk->thread.regs) {
|
|
|
|
|
preempt_disable();
|
|
|
|
|
if (tsk->thread.regs->msr & MSR_VEC) {
|
|
|
|
|
#ifdef CONFIG_SMP
|
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|
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BUG_ON(tsk != current);
|
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|
|
#endif
|
2007-08-29 02:15:53 +00:00
|
|
|
giveup_altivec(tsk);
|
2005-09-26 06:04:21 +00:00
|
|
|
}
|
|
|
|
|
preempt_enable();
|
|
|
|
|
}
|
|
|
|
|
}
|
KVM: PPC: Add support for Book3S processors in hypervisor mode
This adds support for KVM running on 64-bit Book 3S processors,
specifically POWER7, in hypervisor mode. Using hypervisor mode means
that the guest can use the processor's supervisor mode. That means
that the guest can execute privileged instructions and access privileged
registers itself without trapping to the host. This gives excellent
performance, but does mean that KVM cannot emulate a processor
architecture other than the one that the hardware implements.
This code assumes that the guest is running paravirtualized using the
PAPR (Power Architecture Platform Requirements) interface, which is the
interface that IBM's PowerVM hypervisor uses. That means that existing
Linux distributions that run on IBM pSeries machines will also run
under KVM without modification. In order to communicate the PAPR
hypercalls to qemu, this adds a new KVM_EXIT_PAPR_HCALL exit code
to include/linux/kvm.h.
Currently the choice between book3s_hv support and book3s_pr support
(i.e. the existing code, which runs the guest in user mode) has to be
made at kernel configuration time, so a given kernel binary can only
do one or the other.
This new book3s_hv code doesn't support MMIO emulation at present.
Since we are running paravirtualized guests, this isn't a serious
restriction.
With the guest running in supervisor mode, most exceptions go straight
to the guest. We will never get data or instruction storage or segment
interrupts, alignment interrupts, decrementer interrupts, program
interrupts, single-step interrupts, etc., coming to the hypervisor from
the guest. Therefore this introduces a new KVMTEST_NONHV macro for the
exception entry path so that we don't have to do the KVM test on entry
to those exception handlers.
We do however get hypervisor decrementer, hypervisor data storage,
hypervisor instruction storage, and hypervisor emulation assist
interrupts, so we have to handle those.
In hypervisor mode, real-mode accesses can access all of RAM, not just
a limited amount. Therefore we put all the guest state in the vcpu.arch
and use the shadow_vcpu in the PACA only for temporary scratch space.
We allocate the vcpu with kzalloc rather than vzalloc, and we don't use
anything in the kvmppc_vcpu_book3s struct, so we don't allocate it.
We don't have a shared page with the guest, but we still need a
kvm_vcpu_arch_shared struct to store the values of various registers,
so we include one in the vcpu_arch struct.
The POWER7 processor has a restriction that all threads in a core have
to be in the same partition. MMU-on kernel code counts as a partition
(partition 0), so we have to do a partition switch on every entry to and
exit from the guest. At present we require the host and guest to run
in single-thread mode because of this hardware restriction.
This code allocates a hashed page table for the guest and initializes
it with HPTEs for the guest's Virtual Real Memory Area (VRMA). We
require that the guest memory is allocated using 16MB huge pages, in
order to simplify the low-level memory management. This also means that
we can get away without tracking paging activity in the host for now,
since huge pages can't be paged or swapped.
This also adds a few new exports needed by the book3s_hv code.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-06-29 00:21:34 +00:00
|
|
|
EXPORT_SYMBOL_GPL(flush_altivec_to_thread);
|
2005-09-26 06:04:21 +00:00
|
|
|
#endif /* CONFIG_ALTIVEC */
|
|
|
|
|
|
2008-06-25 04:07:18 +00:00
|
|
|
#ifdef CONFIG_VSX
|
|
|
|
|
#if 0
|
|
|
|
|
/* not currently used, but some crazy RAID module might want to later */
|
|
|
|
|
void enable_kernel_vsx(void)
|
|
|
|
|
{
|
|
|
|
|
WARN_ON(preemptible());
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
|
if (current->thread.regs && (current->thread.regs->msr & MSR_VSX))
|
|
|
|
|
giveup_vsx(current);
|
|
|
|
|
else
|
|
|
|
|
giveup_vsx(NULL); /* just enable vsx for kernel - force */
|
|
|
|
|
#else
|
|
|
|
|
giveup_vsx(last_task_used_vsx);
|
|
|
|
|
#endif /* CONFIG_SMP */
|
|
|
|
|
}
|
|
|
|
|
EXPORT_SYMBOL(enable_kernel_vsx);
|
|
|
|
|
#endif
|
|
|
|
|
|
2008-07-11 06:29:12 +00:00
|
|
|
void giveup_vsx(struct task_struct *tsk)
|
|
|
|
|
{
|
|
|
|
|
giveup_fpu(tsk);
|
|
|
|
|
giveup_altivec(tsk);
|
|
|
|
|
__giveup_vsx(tsk);
|
|
|
|
|
}
|
|
|
|
|
|
2008-06-25 04:07:18 +00:00
|
|
|
void flush_vsx_to_thread(struct task_struct *tsk)
|
|
|
|
|
{
|
|
|
|
|
if (tsk->thread.regs) {
|
|
|
|
|
preempt_disable();
|
|
|
|
|
if (tsk->thread.regs->msr & MSR_VSX) {
|
|
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
|
BUG_ON(tsk != current);
|
|
|
|
|
#endif
|
|
|
|
|
giveup_vsx(tsk);
|
|
|
|
|
}
|
|
|
|
|
preempt_enable();
|
|
|
|
|
}
|
|
|
|
|
}
|
KVM: PPC: Add support for Book3S processors in hypervisor mode
This adds support for KVM running on 64-bit Book 3S processors,
specifically POWER7, in hypervisor mode. Using hypervisor mode means
that the guest can use the processor's supervisor mode. That means
that the guest can execute privileged instructions and access privileged
registers itself without trapping to the host. This gives excellent
performance, but does mean that KVM cannot emulate a processor
architecture other than the one that the hardware implements.
This code assumes that the guest is running paravirtualized using the
PAPR (Power Architecture Platform Requirements) interface, which is the
interface that IBM's PowerVM hypervisor uses. That means that existing
Linux distributions that run on IBM pSeries machines will also run
under KVM without modification. In order to communicate the PAPR
hypercalls to qemu, this adds a new KVM_EXIT_PAPR_HCALL exit code
to include/linux/kvm.h.
Currently the choice between book3s_hv support and book3s_pr support
(i.e. the existing code, which runs the guest in user mode) has to be
made at kernel configuration time, so a given kernel binary can only
do one or the other.
This new book3s_hv code doesn't support MMIO emulation at present.
Since we are running paravirtualized guests, this isn't a serious
restriction.
With the guest running in supervisor mode, most exceptions go straight
to the guest. We will never get data or instruction storage or segment
interrupts, alignment interrupts, decrementer interrupts, program
interrupts, single-step interrupts, etc., coming to the hypervisor from
the guest. Therefore this introduces a new KVMTEST_NONHV macro for the
exception entry path so that we don't have to do the KVM test on entry
to those exception handlers.
We do however get hypervisor decrementer, hypervisor data storage,
hypervisor instruction storage, and hypervisor emulation assist
interrupts, so we have to handle those.
In hypervisor mode, real-mode accesses can access all of RAM, not just
a limited amount. Therefore we put all the guest state in the vcpu.arch
and use the shadow_vcpu in the PACA only for temporary scratch space.
We allocate the vcpu with kzalloc rather than vzalloc, and we don't use
anything in the kvmppc_vcpu_book3s struct, so we don't allocate it.
We don't have a shared page with the guest, but we still need a
kvm_vcpu_arch_shared struct to store the values of various registers,
so we include one in the vcpu_arch struct.
The POWER7 processor has a restriction that all threads in a core have
to be in the same partition. MMU-on kernel code counts as a partition
(partition 0), so we have to do a partition switch on every entry to and
exit from the guest. At present we require the host and guest to run
in single-thread mode because of this hardware restriction.
This code allocates a hashed page table for the guest and initializes
it with HPTEs for the guest's Virtual Real Memory Area (VRMA). We
require that the guest memory is allocated using 16MB huge pages, in
order to simplify the low-level memory management. This also means that
we can get away without tracking paging activity in the host for now,
since huge pages can't be paged or swapped.
This also adds a few new exports needed by the book3s_hv code.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-06-29 00:21:34 +00:00
|
|
|
EXPORT_SYMBOL_GPL(flush_vsx_to_thread);
|
2008-06-25 04:07:18 +00:00
|
|
|
#endif /* CONFIG_VSX */
|
|
|
|
|
|
2005-09-26 06:04:21 +00:00
|
|
|
#ifdef CONFIG_SPE
|
|
|
|
|
|
|
|
|
|
void enable_kernel_spe(void)
|
|
|
|
|
{
|
|
|
|
|
WARN_ON(preemptible());
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
|
if (current->thread.regs && (current->thread.regs->msr & MSR_SPE))
|
|
|
|
|
giveup_spe(current);
|
|
|
|
|
else
|
|
|
|
|
giveup_spe(NULL); /* just enable SPE for kernel - force */
|
|
|
|
|
#else
|
|
|
|
|
giveup_spe(last_task_used_spe);
|
|
|
|
|
#endif /* __SMP __ */
|
|
|
|
|
}
|
|
|
|
|
EXPORT_SYMBOL(enable_kernel_spe);
|
|
|
|
|
|
|
|
|
|
void flush_spe_to_thread(struct task_struct *tsk)
|
|
|
|
|
{
|
|
|
|
|
if (tsk->thread.regs) {
|
|
|
|
|
preempt_disable();
|
|
|
|
|
if (tsk->thread.regs->msr & MSR_SPE) {
|
|
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
|
BUG_ON(tsk != current);
|
|
|
|
|
#endif
|
2011-06-14 23:34:25 +00:00
|
|
|
tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
|
2007-08-29 02:15:53 +00:00
|
|
|
giveup_spe(tsk);
|
2005-09-26 06:04:21 +00:00
|
|
|
}
|
|
|
|
|
preempt_enable();
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
#endif /* CONFIG_SPE */
|
|
|
|
|
|
2006-01-11 11:11:39 +00:00
|
|
|
#ifndef CONFIG_SMP
|
2005-11-30 02:20:54 +00:00
|
|
|
/*
|
|
|
|
|
* If we are doing lazy switching of CPU state (FP, altivec or SPE),
|
|
|
|
|
* and the current task has some state, discard it.
|
|
|
|
|
*/
|
2006-01-11 11:11:39 +00:00
|
|
|
void discard_lazy_cpu_state(void)
|
2005-11-30 02:20:54 +00:00
|
|
|
{
|
|
|
|
|
preempt_disable();
|
|
|
|
|
if (last_task_used_math == current)
|
|
|
|
|
last_task_used_math = NULL;
|
|
|
|
|
#ifdef CONFIG_ALTIVEC
|
|
|
|
|
if (last_task_used_altivec == current)
|
|
|
|
|
last_task_used_altivec = NULL;
|
|
|
|
|
#endif /* CONFIG_ALTIVEC */
|
2008-06-25 04:07:18 +00:00
|
|
|
#ifdef CONFIG_VSX
|
|
|
|
|
if (last_task_used_vsx == current)
|
|
|
|
|
last_task_used_vsx = NULL;
|
|
|
|
|
#endif /* CONFIG_VSX */
|
2005-11-30 02:20:54 +00:00
|
|
|
#ifdef CONFIG_SPE
|
|
|
|
|
if (last_task_used_spe == current)
|
|
|
|
|
last_task_used_spe = NULL;
|
|
|
|
|
#endif
|
|
|
|
|
preempt_enable();
|
|
|
|
|
}
|
2006-01-11 11:11:39 +00:00
|
|
|
#endif /* CONFIG_SMP */
|
2005-11-30 02:20:54 +00:00
|
|
|
|
2010-02-08 11:51:18 +00:00
|
|
|
#ifdef CONFIG_PPC_ADV_DEBUG_REGS
|
|
|
|
|
void do_send_trap(struct pt_regs *regs, unsigned long address,
|
|
|
|
|
unsigned long error_code, int signal_code, int breakpt)
|
|
|
|
|
{
|
|
|
|
|
siginfo_t info;
|
|
|
|
|
|
2012-08-23 21:27:09 +00:00
|
|
|
current->thread.trap_nr = signal_code;
|
2010-02-08 11:51:18 +00:00
|
|
|
if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
|
|
|
|
|
11, SIGSEGV) == NOTIFY_STOP)
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
/* Deliver the signal to userspace */
|
|
|
|
|
info.si_signo = SIGTRAP;
|
|
|
|
|
info.si_errno = breakpt; /* breakpoint or watchpoint id */
|
|
|
|
|
info.si_code = signal_code;
|
|
|
|
|
info.si_addr = (void __user *)address;
|
|
|
|
|
force_sig_info(SIGTRAP, &info, current);
|
|
|
|
|
}
|
|
|
|
|
#else /* !CONFIG_PPC_ADV_DEBUG_REGS */
|
2008-07-23 16:10:41 +00:00
|
|
|
void do_dabr(struct pt_regs *regs, unsigned long address,
|
|
|
|
|
unsigned long error_code)
|
|
|
|
|
{
|
|
|
|
|
siginfo_t info;
|
|
|
|
|
|
2012-08-23 21:27:09 +00:00
|
|
|
current->thread.trap_nr = TRAP_HWBKPT;
|
2008-07-23 16:10:41 +00:00
|
|
|
if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
|
|
|
|
|
11, SIGSEGV) == NOTIFY_STOP)
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
if (debugger_dabr_match(regs))
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
/* Clear the DABR */
|
2012-09-06 21:24:56 +00:00
|
|
|
set_dabr(0, 0);
|
2008-07-23 16:10:41 +00:00
|
|
|
|
|
|
|
|
/* Deliver the signal to userspace */
|
|
|
|
|
info.si_signo = SIGTRAP;
|
|
|
|
|
info.si_errno = 0;
|
|
|
|
|
info.si_code = TRAP_HWBKPT;
|
|
|
|
|
info.si_addr = (void __user *)address;
|
|
|
|
|
force_sig_info(SIGTRAP, &info, current);
|
|
|
|
|
}
|
2010-02-08 11:51:18 +00:00
|
|
|
#endif /* CONFIG_PPC_ADV_DEBUG_REGS */
|
2008-07-23 16:10:41 +00:00
|
|
|
|
2008-03-28 08:11:48 +00:00
|
|
|
static DEFINE_PER_CPU(unsigned long, current_dabr);
|
|
|
|
|
|
2010-02-08 11:51:18 +00:00
|
|
|
#ifdef CONFIG_PPC_ADV_DEBUG_REGS
|
|
|
|
|
/*
|
|
|
|
|
* Set the debug registers back to their default "safe" values.
|
|
|
|
|
*/
|
|
|
|
|
static void set_debug_reg_defaults(struct thread_struct *thread)
|
|
|
|
|
{
|
|
|
|
|
thread->iac1 = thread->iac2 = 0;
|
|
|
|
|
#if CONFIG_PPC_ADV_DEBUG_IACS > 2
|
|
|
|
|
thread->iac3 = thread->iac4 = 0;
|
|
|
|
|
#endif
|
|
|
|
|
thread->dac1 = thread->dac2 = 0;
|
|
|
|
|
#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
|
|
|
|
|
thread->dvc1 = thread->dvc2 = 0;
|
|
|
|
|
#endif
|
|
|
|
|
thread->dbcr0 = 0;
|
|
|
|
|
#ifdef CONFIG_BOOKE
|
|
|
|
|
/*
|
|
|
|
|
* Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
|
|
|
|
|
*/
|
|
|
|
|
thread->dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US | \
|
|
|
|
|
DBCR1_IAC3US | DBCR1_IAC4US;
|
|
|
|
|
/*
|
|
|
|
|
* Force Data Address Compare User/Supervisor bits to be User-only
|
|
|
|
|
* (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
|
|
|
|
|
*/
|
|
|
|
|
thread->dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
|
|
|
|
|
#else
|
|
|
|
|
thread->dbcr1 = 0;
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void prime_debug_regs(struct thread_struct *thread)
|
|
|
|
|
{
|
|
|
|
|
mtspr(SPRN_IAC1, thread->iac1);
|
|
|
|
|
mtspr(SPRN_IAC2, thread->iac2);
|
|
|
|
|
#if CONFIG_PPC_ADV_DEBUG_IACS > 2
|
|
|
|
|
mtspr(SPRN_IAC3, thread->iac3);
|
|
|
|
|
mtspr(SPRN_IAC4, thread->iac4);
|
|
|
|
|
#endif
|
|
|
|
|
mtspr(SPRN_DAC1, thread->dac1);
|
|
|
|
|
mtspr(SPRN_DAC2, thread->dac2);
|
|
|
|
|
#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
|
|
|
|
|
mtspr(SPRN_DVC1, thread->dvc1);
|
|
|
|
|
mtspr(SPRN_DVC2, thread->dvc2);
|
|
|
|
|
#endif
|
|
|
|
|
mtspr(SPRN_DBCR0, thread->dbcr0);
|
|
|
|
|
mtspr(SPRN_DBCR1, thread->dbcr1);
|
|
|
|
|
#ifdef CONFIG_BOOKE
|
|
|
|
|
mtspr(SPRN_DBCR2, thread->dbcr2);
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
/*
|
|
|
|
|
* Unless neither the old or new thread are making use of the
|
|
|
|
|
* debug registers, set the debug registers from the values
|
|
|
|
|
* stored in the new thread.
|
|
|
|
|
*/
|
|
|
|
|
static void switch_booke_debug_regs(struct thread_struct *new_thread)
|
|
|
|
|
{
|
|
|
|
|
if ((current->thread.dbcr0 & DBCR0_IDM)
|
|
|
|
|
|| (new_thread->dbcr0 & DBCR0_IDM))
|
|
|
|
|
prime_debug_regs(new_thread);
|
|
|
|
|
}
|
|
|
|
|
#else /* !CONFIG_PPC_ADV_DEBUG_REGS */
|
2011-02-10 04:44:35 +00:00
|
|
|
#ifndef CONFIG_HAVE_HW_BREAKPOINT
|
2010-02-08 11:51:18 +00:00
|
|
|
static void set_debug_reg_defaults(struct thread_struct *thread)
|
|
|
|
|
{
|
|
|
|
|
if (thread->dabr) {
|
|
|
|
|
thread->dabr = 0;
|
2012-09-06 21:24:56 +00:00
|
|
|
thread->dabrx = 0;
|
|
|
|
|
set_dabr(0, 0);
|
2010-02-08 11:51:18 +00:00
|
|
|
}
|
|
|
|
|
}
|
2011-02-10 04:44:35 +00:00
|
|
|
#endif /* !CONFIG_HAVE_HW_BREAKPOINT */
|
2010-02-08 11:51:18 +00:00
|
|
|
#endif /* CONFIG_PPC_ADV_DEBUG_REGS */
|
|
|
|
|
|
2012-09-06 21:24:56 +00:00
|
|
|
int set_dabr(unsigned long dabr, unsigned long dabrx)
|
2005-09-26 06:04:21 +00:00
|
|
|
{
|
2008-03-28 08:11:48 +00:00
|
|
|
__get_cpu_var(current_dabr) = dabr;
|
|
|
|
|
|
2005-11-03 04:30:49 +00:00
|
|
|
if (ppc_md.set_dabr)
|
2012-09-06 21:24:56 +00:00
|
|
|
return ppc_md.set_dabr(dabr, dabrx);
|
2005-09-26 06:04:21 +00:00
|
|
|
|
2007-06-04 05:15:48 +00:00
|
|
|
/* XXX should we have a CPU_FTR_HAS_DABR ? */
|
2010-02-08 11:50:57 +00:00
|
|
|
#ifdef CONFIG_PPC_ADV_DEBUG_REGS
|
2008-07-23 16:10:41 +00:00
|
|
|
mtspr(SPRN_DAC1, dabr);
|
2010-03-05 10:43:24 +00:00
|
|
|
#ifdef CONFIG_PPC_47x
|
|
|
|
|
isync();
|
|
|
|
|
#endif
|
2009-09-08 14:16:58 +00:00
|
|
|
#elif defined(CONFIG_PPC_BOOK3S)
|
|
|
|
|
mtspr(SPRN_DABR, dabr);
|
2012-09-06 21:24:56 +00:00
|
|
|
mtspr(SPRN_DABRX, dabrx);
|
2008-07-23 16:10:41 +00:00
|
|
|
#endif
|
2005-11-03 04:30:49 +00:00
|
|
|
return 0;
|
2005-09-26 06:04:21 +00:00
|
|
|
}
|
|
|
|
|
|
2005-10-10 12:29:05 +00:00
|
|
|
#ifdef CONFIG_PPC64
|
|
|
|
|
DEFINE_PER_CPU(struct cpu_usage, cpu_usage_array);
|
|
|
|
|
#endif
|
2005-09-26 06:04:21 +00:00
|
|
|
|
|
|
|
|
struct task_struct *__switch_to(struct task_struct *prev,
|
|
|
|
|
struct task_struct *new)
|
|
|
|
|
{
|
|
|
|
|
struct thread_struct *new_thread, *old_thread;
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
struct task_struct *last;
|
2011-05-25 00:11:48 +00:00
|
|
|
#ifdef CONFIG_PPC_BOOK3S_64
|
|
|
|
|
struct ppc64_tlb_batch *batch;
|
|
|
|
|
#endif
|
2005-09-26 06:04:21 +00:00
|
|
|
|
|
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
|
/* avoid complexity of lazy save/restore of fpu
|
|
|
|
|
* by just saving it every time we switch out if
|
|
|
|
|
* this task used the fpu during the last quantum.
|
|
|
|
|
*
|
|
|
|
|
* If it tries to use the fpu again, it'll trap and
|
|
|
|
|
* reload its fp regs. So we don't have to do a restore
|
|
|
|
|
* every switch, just a save.
|
|
|
|
|
* -- Cort
|
|
|
|
|
*/
|
|
|
|
|
if (prev->thread.regs && (prev->thread.regs->msr & MSR_FP))
|
|
|
|
|
giveup_fpu(prev);
|
|
|
|
|
#ifdef CONFIG_ALTIVEC
|
|
|
|
|
/*
|
|
|
|
|
* If the previous thread used altivec in the last quantum
|
|
|
|
|
* (thus changing altivec regs) then save them.
|
|
|
|
|
* We used to check the VRSAVE register but not all apps
|
|
|
|
|
* set it, so we don't rely on it now (and in fact we need
|
|
|
|
|
* to save & restore VSCR even if VRSAVE == 0). -- paulus
|
|
|
|
|
*
|
|
|
|
|
* On SMP we always save/restore altivec regs just to avoid the
|
|
|
|
|
* complexity of changing processors.
|
|
|
|
|
* -- Cort
|
|
|
|
|
*/
|
|
|
|
|
if (prev->thread.regs && (prev->thread.regs->msr & MSR_VEC))
|
|
|
|
|
giveup_altivec(prev);
|
|
|
|
|
#endif /* CONFIG_ALTIVEC */
|
2008-06-25 04:07:18 +00:00
|
|
|
#ifdef CONFIG_VSX
|
|
|
|
|
if (prev->thread.regs && (prev->thread.regs->msr & MSR_VSX))
|
2008-07-11 06:29:12 +00:00
|
|
|
/* VMX and FPU registers are already save here */
|
|
|
|
|
__giveup_vsx(prev);
|
2008-06-25 04:07:18 +00:00
|
|
|
#endif /* CONFIG_VSX */
|
2005-09-26 06:04:21 +00:00
|
|
|
#ifdef CONFIG_SPE
|
|
|
|
|
/*
|
|
|
|
|
* If the previous thread used spe in the last quantum
|
|
|
|
|
* (thus changing spe regs) then save them.
|
|
|
|
|
*
|
|
|
|
|
* On SMP we always save/restore spe regs just to avoid the
|
|
|
|
|
* complexity of changing processors.
|
|
|
|
|
*/
|
|
|
|
|
if ((prev->thread.regs && (prev->thread.regs->msr & MSR_SPE)))
|
|
|
|
|
giveup_spe(prev);
|
2005-10-01 03:49:08 +00:00
|
|
|
#endif /* CONFIG_SPE */
|
|
|
|
|
|
|
|
|
|
#else /* CONFIG_SMP */
|
|
|
|
|
#ifdef CONFIG_ALTIVEC
|
|
|
|
|
/* Avoid the trap. On smp this this never happens since
|
|
|
|
|
* we don't set last_task_used_altivec -- Cort
|
|
|
|
|
*/
|
|
|
|
|
if (new->thread.regs && last_task_used_altivec == new)
|
|
|
|
|
new->thread.regs->msr |= MSR_VEC;
|
|
|
|
|
#endif /* CONFIG_ALTIVEC */
|
2008-06-25 04:07:18 +00:00
|
|
|
#ifdef CONFIG_VSX
|
|
|
|
|
if (new->thread.regs && last_task_used_vsx == new)
|
|
|
|
|
new->thread.regs->msr |= MSR_VSX;
|
|
|
|
|
#endif /* CONFIG_VSX */
|
2005-10-01 03:49:08 +00:00
|
|
|
#ifdef CONFIG_SPE
|
2005-09-26 06:04:21 +00:00
|
|
|
/* Avoid the trap. On smp this this never happens since
|
|
|
|
|
* we don't set last_task_used_spe
|
|
|
|
|
*/
|
|
|
|
|
if (new->thread.regs && last_task_used_spe == new)
|
|
|
|
|
new->thread.regs->msr |= MSR_SPE;
|
|
|
|
|
#endif /* CONFIG_SPE */
|
2005-10-01 03:49:08 +00:00
|
|
|
|
2005-09-26 06:04:21 +00:00
|
|
|
#endif /* CONFIG_SMP */
|
|
|
|
|
|
2010-02-08 11:50:57 +00:00
|
|
|
#ifdef CONFIG_PPC_ADV_DEBUG_REGS
|
2010-02-08 11:51:18 +00:00
|
|
|
switch_booke_debug_regs(&new->thread);
|
2009-09-08 14:16:58 +00:00
|
|
|
#else
|
2010-06-15 06:05:19 +00:00
|
|
|
/*
|
|
|
|
|
* For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
|
|
|
|
|
* schedule DABR
|
|
|
|
|
*/
|
|
|
|
|
#ifndef CONFIG_HAVE_HW_BREAKPOINT
|
2009-09-08 14:16:58 +00:00
|
|
|
if (unlikely(__get_cpu_var(current_dabr) != new->thread.dabr))
|
2012-09-06 21:24:56 +00:00
|
|
|
set_dabr(new->thread.dabr, new->thread.dabrx);
|
2010-06-15 06:05:19 +00:00
|
|
|
#endif /* CONFIG_HAVE_HW_BREAKPOINT */
|
2008-07-23 16:10:41 +00:00
|
|
|
#endif
|
|
|
|
|
|
2009-09-08 14:16:58 +00:00
|
|
|
|
2005-09-26 06:04:21 +00:00
|
|
|
new_thread = &new->thread;
|
|
|
|
|
old_thread = ¤t->thread;
|
2005-10-10 12:29:05 +00:00
|
|
|
|
|
|
|
|
#ifdef CONFIG_PPC64
|
|
|
|
|
/*
|
|
|
|
|
* Collect processor utilization data per process
|
|
|
|
|
*/
|
|
|
|
|
if (firmware_has_feature(FW_FEATURE_SPLPAR)) {
|
|
|
|
|
struct cpu_usage *cu = &__get_cpu_var(cpu_usage_array);
|
|
|
|
|
long unsigned start_tb, current_tb;
|
|
|
|
|
start_tb = old_thread->start_tb;
|
|
|
|
|
cu->current_tb = current_tb = mfspr(SPRN_PURR);
|
|
|
|
|
old_thread->accum_tb += (current_tb - start_tb);
|
|
|
|
|
new_thread->start_tb = current_tb;
|
|
|
|
|
}
|
2011-05-25 00:11:48 +00:00
|
|
|
#endif /* CONFIG_PPC64 */
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_PPC_BOOK3S_64
|
|
|
|
|
batch = &__get_cpu_var(ppc64_tlb_batch);
|
|
|
|
|
if (batch->active) {
|
|
|
|
|
current_thread_info()->local_flags |= _TLF_LAZY_MMU;
|
|
|
|
|
if (batch->index)
|
|
|
|
|
__flush_tlb_pending(batch);
|
|
|
|
|
batch->active = 0;
|
|
|
|
|
}
|
|
|
|
|
#endif /* CONFIG_PPC_BOOK3S_64 */
|
2005-10-10 12:29:05 +00:00
|
|
|
|
2005-09-26 06:04:21 +00:00
|
|
|
local_irq_save(flags);
|
powerpc: Implement accurate task and CPU time accounting
This implements accurate task and cpu time accounting for 64-bit
powerpc kernels. Instead of accounting a whole jiffy of time to a
task on a timer interrupt because that task happened to be running at
the time, we now account time in units of timebase ticks according to
the actual time spent by the task in user mode and kernel mode. We
also count the time spent processing hardware and software interrupts
accurately. This is conditional on CONFIG_VIRT_CPU_ACCOUNTING. If
that is not set, we do tick-based approximate accounting as before.
To get this accurate information, we read either the PURR (processor
utilization of resources register) on POWER5 machines, or the timebase
on other machines on
* each entry to the kernel from usermode
* each exit to usermode
* transitions between process context, hard irq context and soft irq
context in kernel mode
* context switches.
On POWER5 systems with shared-processor logical partitioning we also
read both the PURR and the timebase at each timer interrupt and
context switch in order to determine how much time has been taken by
the hypervisor to run other partitions ("steal" time). Unfortunately,
since we need values of the PURR on both threads at the same time to
accurately calculate the steal time, and since we can only calculate
steal time on a per-core basis, the apportioning of the steal time
between idle time (time which we ceded to the hypervisor in the idle
loop) and actual stolen time is somewhat approximate at the moment.
This is all based quite heavily on what s390 does, and it uses the
generic interfaces that were added by the s390 developers,
i.e. account_system_time(), account_user_time(), etc.
This patch doesn't add any new interfaces between the kernel and
userspace, and doesn't change the units in which time is reported to
userspace by things such as /proc/stat, /proc/<pid>/stat, getrusage(),
times(), etc. Internally the various task and cpu times are stored in
timebase units, but they are converted to USER_HZ units (1/100th of a
second) when reported to userspace. Some precision is therefore lost
but there should not be any accumulating error, since the internal
accumulation is at full precision.
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-02-23 23:06:59 +00:00
|
|
|
|
2008-03-17 04:27:09 +00:00
|
|
|
/*
|
|
|
|
|
* We can't take a PMU exception inside _switch() since there is a
|
|
|
|
|
* window where the kernel stack SLB and the kernel stack are out
|
|
|
|
|
* of sync. Hard disable here.
|
|
|
|
|
*/
|
|
|
|
|
hard_irq_disable();
|
2005-09-26 06:04:21 +00:00
|
|
|
last = _switch(old_thread, new_thread);
|
|
|
|
|
|
2011-05-25 00:11:48 +00:00
|
|
|
#ifdef CONFIG_PPC_BOOK3S_64
|
|
|
|
|
if (current_thread_info()->local_flags & _TLF_LAZY_MMU) {
|
|
|
|
|
current_thread_info()->local_flags &= ~_TLF_LAZY_MMU;
|
|
|
|
|
batch = &__get_cpu_var(ppc64_tlb_batch);
|
|
|
|
|
batch->active = 1;
|
|
|
|
|
}
|
|
|
|
|
#endif /* CONFIG_PPC_BOOK3S_64 */
|
|
|
|
|
|
2005-09-26 06:04:21 +00:00
|
|
|
local_irq_restore(flags);
|
|
|
|
|
|
|
|
|
|
return last;
|
|
|
|
|
}
|
|
|
|
|
|
2005-10-10 12:29:05 +00:00
|
|
|
static int instructions_to_print = 16;
|
|
|
|
|
|
|
|
|
|
static void show_instructions(struct pt_regs *regs)
|
|
|
|
|
{
|
|
|
|
|
int i;
|
|
|
|
|
unsigned long pc = regs->nip - (instructions_to_print * 3 / 4 *
|
|
|
|
|
sizeof(int));
|
|
|
|
|
|
|
|
|
|
printk("Instruction dump:");
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < instructions_to_print; i++) {
|
|
|
|
|
int instr;
|
|
|
|
|
|
|
|
|
|
if (!(i % 8))
|
|
|
|
|
printk("\n");
|
|
|
|
|
|
2007-09-27 18:38:55 +00:00
|
|
|
#if !defined(CONFIG_BOOKE)
|
|
|
|
|
/* If executing with the IMMU off, adjust pc rather
|
|
|
|
|
* than print XXXXXXXX.
|
|
|
|
|
*/
|
|
|
|
|
if (!(regs->msr & MSR_IR))
|
|
|
|
|
pc = (unsigned long)phys_to_virt(pc);
|
|
|
|
|
#endif
|
|
|
|
|
|
2006-03-23 06:38:10 +00:00
|
|
|
/* We use __get_user here *only* to avoid an OOPS on a
|
|
|
|
|
* bad address because the pc *should* only be a
|
|
|
|
|
* kernel address.
|
|
|
|
|
*/
|
2006-10-13 02:17:16 +00:00
|
|
|
if (!__kernel_text_address(pc) ||
|
|
|
|
|
__get_user(instr, (unsigned int __user *)pc)) {
|
2012-01-06 12:34:07 +00:00
|
|
|
printk(KERN_CONT "XXXXXXXX ");
|
2005-10-10 12:29:05 +00:00
|
|
|
} else {
|
|
|
|
|
if (regs->nip == pc)
|
2012-01-06 12:34:07 +00:00
|
|
|
printk(KERN_CONT "<%08x> ", instr);
|
2005-10-10 12:29:05 +00:00
|
|
|
else
|
2012-01-06 12:34:07 +00:00
|
|
|
printk(KERN_CONT "%08x ", instr);
|
2005-10-10 12:29:05 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
pc += sizeof(int);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
printk("\n");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static struct regbit {
|
|
|
|
|
unsigned long bit;
|
|
|
|
|
const char *name;
|
|
|
|
|
} msr_bits[] = {
|
2011-11-24 19:35:57 +00:00
|
|
|
#if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
|
|
|
|
|
{MSR_SF, "SF"},
|
|
|
|
|
{MSR_HV, "HV"},
|
|
|
|
|
#endif
|
|
|
|
|
{MSR_VEC, "VEC"},
|
|
|
|
|
{MSR_VSX, "VSX"},
|
|
|
|
|
#ifdef CONFIG_BOOKE
|
|
|
|
|
{MSR_CE, "CE"},
|
|
|
|
|
#endif
|
2005-10-10 12:29:05 +00:00
|
|
|
{MSR_EE, "EE"},
|
|
|
|
|
{MSR_PR, "PR"},
|
|
|
|
|
{MSR_FP, "FP"},
|
|
|
|
|
{MSR_ME, "ME"},
|
2011-11-24 19:35:57 +00:00
|
|
|
#ifdef CONFIG_BOOKE
|
2008-11-19 04:39:53 +00:00
|
|
|
{MSR_DE, "DE"},
|
2011-11-24 19:35:57 +00:00
|
|
|
#else
|
|
|
|
|
{MSR_SE, "SE"},
|
|
|
|
|
{MSR_BE, "BE"},
|
|
|
|
|
#endif
|
2005-10-10 12:29:05 +00:00
|
|
|
{MSR_IR, "IR"},
|
|
|
|
|
{MSR_DR, "DR"},
|
2011-11-24 19:35:57 +00:00
|
|
|
{MSR_PMM, "PMM"},
|
|
|
|
|
#ifndef CONFIG_BOOKE
|
|
|
|
|
{MSR_RI, "RI"},
|
|
|
|
|
{MSR_LE, "LE"},
|
|
|
|
|
#endif
|
2005-10-10 12:29:05 +00:00
|
|
|
{0, NULL}
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static void printbits(unsigned long val, struct regbit *bits)
|
|
|
|
|
{
|
|
|
|
|
const char *sep = "";
|
|
|
|
|
|
|
|
|
|
printk("<");
|
|
|
|
|
for (; bits->bit; ++bits)
|
|
|
|
|
if (val & bits->bit) {
|
|
|
|
|
printk("%s%s", sep, bits->name);
|
|
|
|
|
sep = ",";
|
|
|
|
|
}
|
|
|
|
|
printk(">");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_PPC64
|
2007-03-21 01:38:19 +00:00
|
|
|
#define REG "%016lx"
|
2005-10-10 12:29:05 +00:00
|
|
|
#define REGS_PER_LINE 4
|
|
|
|
|
#define LAST_VOLATILE 13
|
|
|
|
|
#else
|
2007-03-21 01:38:19 +00:00
|
|
|
#define REG "%08lx"
|
2005-10-10 12:29:05 +00:00
|
|
|
#define REGS_PER_LINE 8
|
|
|
|
|
#define LAST_VOLATILE 12
|
|
|
|
|
#endif
|
|
|
|
|
|
2005-09-26 06:04:21 +00:00
|
|
|
void show_regs(struct pt_regs * regs)
|
|
|
|
|
{
|
|
|
|
|
int i, trap;
|
|
|
|
|
|
2005-10-10 12:29:05 +00:00
|
|
|
printk("NIP: "REG" LR: "REG" CTR: "REG"\n",
|
|
|
|
|
regs->nip, regs->link, regs->ctr);
|
|
|
|
|
printk("REGS: %p TRAP: %04lx %s (%s)\n",
|
2006-10-02 09:18:13 +00:00
|
|
|
regs, regs->trap, print_tainted(), init_utsname()->release);
|
2005-10-10 12:29:05 +00:00
|
|
|
printk("MSR: "REG" ", regs->msr);
|
|
|
|
|
printbits(regs->msr, msr_bits);
|
2007-03-21 01:38:19 +00:00
|
|
|
printk(" CR: %08lx XER: %08lx\n", regs->ccr, regs->xer);
|
powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 07:27:59 +00:00
|
|
|
#ifdef CONFIG_PPC64
|
|
|
|
|
printk("SOFTE: %ld\n", regs->softe);
|
|
|
|
|
#endif
|
2005-09-26 06:04:21 +00:00
|
|
|
trap = TRAP(regs);
|
2011-07-14 19:25:12 +00:00
|
|
|
if ((regs->trap != 0xc00) && cpu_has_feature(CPU_FTR_CFAR))
|
|
|
|
|
printk("CFAR: "REG"\n", regs->orig_gpr3);
|
2005-09-26 06:04:21 +00:00
|
|
|
if (trap == 0x300 || trap == 0x600)
|
2011-10-06 02:53:38 +00:00
|
|
|
#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
|
2007-07-26 05:46:15 +00:00
|
|
|
printk("DEAR: "REG", ESR: "REG"\n", regs->dar, regs->dsisr);
|
|
|
|
|
#else
|
2011-01-11 19:44:30 +00:00
|
|
|
printk("DAR: "REG", DSISR: %08lx\n", regs->dar, regs->dsisr);
|
2007-07-26 05:46:15 +00:00
|
|
|
#endif
|
2005-10-10 12:29:05 +00:00
|
|
|
printk("TASK = %p[%d] '%s' THREAD: %p",
|
2007-10-19 06:40:41 +00:00
|
|
|
current, task_pid_nr(current), current->comm, task_thread_info(current));
|
2005-09-26 06:04:21 +00:00
|
|
|
|
|
|
|
|
#ifdef CONFIG_SMP
|
2008-02-08 18:25:13 +00:00
|
|
|
printk(" CPU: %d", raw_smp_processor_id());
|
2005-09-26 06:04:21 +00:00
|
|
|
#endif /* CONFIG_SMP */
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < 32; i++) {
|
2005-10-10 12:29:05 +00:00
|
|
|
if ((i % REGS_PER_LINE) == 0)
|
2009-06-18 22:29:55 +00:00
|
|
|
printk("\nGPR%02d: ", i);
|
2005-10-10 12:29:05 +00:00
|
|
|
printk(REG " ", regs->gpr[i]);
|
|
|
|
|
if (i == LAST_VOLATILE && !FULL_REGS(regs))
|
2005-09-26 06:04:21 +00:00
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
printk("\n");
|
|
|
|
|
#ifdef CONFIG_KALLSYMS
|
|
|
|
|
/*
|
|
|
|
|
* Lookup NIP late so we have the best change of getting the
|
|
|
|
|
* above info out without failing
|
|
|
|
|
*/
|
2008-07-07 03:44:31 +00:00
|
|
|
printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip);
|
|
|
|
|
printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link);
|
2005-09-26 06:04:21 +00:00
|
|
|
#endif
|
|
|
|
|
show_stack(current, (unsigned long *) regs->gpr[1]);
|
2005-10-10 12:29:05 +00:00
|
|
|
if (!user_mode(regs))
|
|
|
|
|
show_instructions(regs);
|
2005-09-26 06:04:21 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void exit_thread(void)
|
|
|
|
|
{
|
2005-11-30 02:20:54 +00:00
|
|
|
discard_lazy_cpu_state();
|
2005-09-26 06:04:21 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void flush_thread(void)
|
|
|
|
|
{
|
2005-11-30 02:20:54 +00:00
|
|
|
discard_lazy_cpu_state();
|
2005-09-26 06:04:21 +00:00
|
|
|
|
2011-02-10 04:44:35 +00:00
|
|
|
#ifdef CONFIG_HAVE_HW_BREAKPOINT
|
2010-06-15 06:05:19 +00:00
|
|
|
flush_ptrace_hw_breakpoint(current);
|
2011-02-10 04:44:35 +00:00
|
|
|
#else /* CONFIG_HAVE_HW_BREAKPOINT */
|
2010-02-08 11:51:18 +00:00
|
|
|
set_debug_reg_defaults(¤t->thread);
|
2011-02-10 04:44:35 +00:00
|
|
|
#endif /* CONFIG_HAVE_HW_BREAKPOINT */
|
2005-09-26 06:04:21 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
|
release_thread(struct task_struct *t)
|
|
|
|
|
{
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
2012-05-16 22:03:51 +00:00
|
|
|
* this gets called so that we can store coprocessor state into memory and
|
|
|
|
|
* copy the current task into the new thread.
|
2005-09-26 06:04:21 +00:00
|
|
|
*/
|
2012-05-16 22:03:51 +00:00
|
|
|
int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
|
2005-09-26 06:04:21 +00:00
|
|
|
{
|
2012-05-16 22:03:51 +00:00
|
|
|
flush_fp_to_thread(src);
|
|
|
|
|
flush_altivec_to_thread(src);
|
|
|
|
|
flush_vsx_to_thread(src);
|
|
|
|
|
flush_spe_to_thread(src);
|
2010-06-15 06:05:19 +00:00
|
|
|
#ifdef CONFIG_HAVE_HW_BREAKPOINT
|
2012-05-16 22:03:51 +00:00
|
|
|
flush_ptrace_hw_breakpoint(src);
|
2010-06-15 06:05:19 +00:00
|
|
|
#endif /* CONFIG_HAVE_HW_BREAKPOINT */
|
2012-05-16 22:03:51 +00:00
|
|
|
|
|
|
|
|
*dst = *src;
|
|
|
|
|
return 0;
|
2005-09-26 06:04:21 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Copy a thread..
|
|
|
|
|
*/
|
2011-03-02 15:18:48 +00:00
|
|
|
extern unsigned long dscr_default; /* defined in arch/powerpc/kernel/sysfs.c */
|
|
|
|
|
|
2009-04-02 23:56:59 +00:00
|
|
|
int copy_thread(unsigned long clone_flags, unsigned long usp,
|
2012-09-12 22:32:42 +00:00
|
|
|
unsigned long arg, struct task_struct *p,
|
2005-10-10 12:29:05 +00:00
|
|
|
struct pt_regs *regs)
|
2005-09-26 06:04:21 +00:00
|
|
|
{
|
|
|
|
|
struct pt_regs *childregs, *kregs;
|
|
|
|
|
extern void ret_from_fork(void);
|
2012-09-12 22:32:42 +00:00
|
|
|
extern void ret_from_kernel_thread(void);
|
|
|
|
|
void (*f)(void);
|
2006-01-12 09:06:02 +00:00
|
|
|
unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE;
|
2005-09-26 06:04:21 +00:00
|
|
|
|
|
|
|
|
/* Copy registers */
|
|
|
|
|
sp -= sizeof(struct pt_regs);
|
|
|
|
|
childregs = (struct pt_regs *) sp;
|
2012-09-12 22:32:42 +00:00
|
|
|
if (!regs) {
|
2005-09-26 06:04:21 +00:00
|
|
|
/* for kernel thread, set `current' and stackptr in new task */
|
2012-09-12 22:32:42 +00:00
|
|
|
memset(childregs, 0, sizeof(struct pt_regs));
|
2005-09-26 06:04:21 +00:00
|
|
|
childregs->gpr[1] = sp + sizeof(struct pt_regs);
|
2012-09-12 22:32:42 +00:00
|
|
|
#ifdef CONFIG_PPC64
|
|
|
|
|
childregs->gpr[14] = *(unsigned long *)usp;
|
|
|
|
|
childregs->gpr[2] = ((unsigned long *)usp)[1],
|
2006-01-12 09:06:01 +00:00
|
|
|
clear_tsk_thread_flag(p, TIF_32BIT);
|
2012-09-12 22:32:42 +00:00
|
|
|
#else
|
|
|
|
|
childregs->gpr[14] = usp; /* function */
|
|
|
|
|
childregs->gpr[2] = (unsigned long) p;
|
2005-10-10 12:29:05 +00:00
|
|
|
#endif
|
2012-09-12 22:32:42 +00:00
|
|
|
childregs->gpr[15] = arg;
|
2005-09-26 06:04:21 +00:00
|
|
|
p->thread.regs = NULL; /* no user register state */
|
2012-09-12 22:32:42 +00:00
|
|
|
f = ret_from_kernel_thread;
|
2005-09-26 06:04:21 +00:00
|
|
|
} else {
|
2012-09-12 22:32:42 +00:00
|
|
|
CHECK_FULL_REGS(regs);
|
|
|
|
|
*childregs = *regs;
|
2005-09-26 06:04:21 +00:00
|
|
|
childregs->gpr[1] = usp;
|
|
|
|
|
p->thread.regs = childregs;
|
2012-09-12 22:32:42 +00:00
|
|
|
childregs->gpr[3] = 0; /* Result from fork() */
|
2005-10-10 12:29:05 +00:00
|
|
|
if (clone_flags & CLONE_SETTLS) {
|
|
|
|
|
#ifdef CONFIG_PPC64
|
2010-07-29 22:04:39 +00:00
|
|
|
if (!is_32bit_task())
|
2005-10-10 12:29:05 +00:00
|
|
|
childregs->gpr[13] = childregs->gpr[6];
|
|
|
|
|
else
|
|
|
|
|
#endif
|
|
|
|
|
childregs->gpr[2] = childregs->gpr[6];
|
|
|
|
|
}
|
2012-09-12 22:32:42 +00:00
|
|
|
|
|
|
|
|
f = ret_from_fork;
|
2005-09-26 06:04:21 +00:00
|
|
|
}
|
|
|
|
|
sp -= STACK_FRAME_OVERHEAD;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* The way this works is that at some point in the future
|
|
|
|
|
* some task will call _switch to switch to the new task.
|
|
|
|
|
* That will pop off the stack frame created below and start
|
|
|
|
|
* the new task running at ret_from_fork. The new task will
|
|
|
|
|
* do some house keeping and then return from the fork or clone
|
|
|
|
|
* system call, using the stack frame created above.
|
|
|
|
|
*/
|
|
|
|
|
sp -= sizeof(struct pt_regs);
|
|
|
|
|
kregs = (struct pt_regs *) sp;
|
|
|
|
|
sp -= STACK_FRAME_OVERHEAD;
|
|
|
|
|
p->thread.ksp = sp;
|
2008-04-28 06:21:22 +00:00
|
|
|
p->thread.ksp_limit = (unsigned long)task_stack_page(p) +
|
|
|
|
|
_ALIGN_UP(sizeof(struct thread_info), 16);
|
2005-09-26 06:04:21 +00:00
|
|
|
|
2009-06-02 21:17:45 +00:00
|
|
|
#ifdef CONFIG_PPC_STD_MMU_64
|
2011-04-06 19:48:50 +00:00
|
|
|
if (mmu_has_feature(MMU_FTR_SLB)) {
|
2007-10-11 10:37:10 +00:00
|
|
|
unsigned long sp_vsid;
|
2005-11-07 00:06:55 +00:00
|
|
|
unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp;
|
2005-10-10 12:29:05 +00:00
|
|
|
|
2011-04-06 19:48:50 +00:00
|
|
|
if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
|
2007-10-11 10:37:10 +00:00
|
|
|
sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T)
|
|
|
|
|
<< SLB_VSID_SHIFT_1T;
|
|
|
|
|
else
|
|
|
|
|
sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M)
|
|
|
|
|
<< SLB_VSID_SHIFT;
|
2005-11-07 00:06:55 +00:00
|
|
|
sp_vsid |= SLB_VSID_KERNEL | llp;
|
2005-10-10 12:29:05 +00:00
|
|
|
p->thread.ksp_vsid = sp_vsid;
|
|
|
|
|
}
|
2009-07-23 23:15:27 +00:00
|
|
|
#endif /* CONFIG_PPC_STD_MMU_64 */
|
2011-03-02 15:18:48 +00:00
|
|
|
#ifdef CONFIG_PPC64
|
|
|
|
|
if (cpu_has_feature(CPU_FTR_DSCR)) {
|
2012-09-03 16:49:47 +00:00
|
|
|
p->thread.dscr_inherit = current->thread.dscr_inherit;
|
|
|
|
|
p->thread.dscr = current->thread.dscr;
|
2011-03-02 15:18:48 +00:00
|
|
|
}
|
|
|
|
|
#endif
|
2005-10-10 12:29:05 +00:00
|
|
|
/*
|
|
|
|
|
* The PPC64 ABI makes use of a TOC to contain function
|
|
|
|
|
* pointers. The function (ret_from_except) is actually a pointer
|
|
|
|
|
* to the TOC entry. The first entry is a pointer to the actual
|
|
|
|
|
* function.
|
2012-09-12 22:32:42 +00:00
|
|
|
*/
|
2009-07-23 23:15:27 +00:00
|
|
|
#ifdef CONFIG_PPC64
|
2012-09-12 22:32:42 +00:00
|
|
|
kregs->nip = *((unsigned long *)f);
|
2005-10-10 12:29:05 +00:00
|
|
|
#else
|
2012-09-12 22:32:42 +00:00
|
|
|
kregs->nip = (unsigned long)f;
|
2005-10-10 12:29:05 +00:00
|
|
|
#endif
|
2005-09-26 06:04:21 +00:00
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Set up a thread for executing a new program
|
|
|
|
|
*/
|
2005-10-10 12:29:05 +00:00
|
|
|
void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp)
|
2005-09-26 06:04:21 +00:00
|
|
|
{
|
2005-10-21 06:01:33 +00:00
|
|
|
#ifdef CONFIG_PPC64
|
|
|
|
|
unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */
|
|
|
|
|
#endif
|
|
|
|
|
|
2005-10-10 12:29:05 +00:00
|
|
|
/*
|
|
|
|
|
* If we exec out of a kernel thread then thread.regs will not be
|
|
|
|
|
* set. Do it now.
|
|
|
|
|
*/
|
|
|
|
|
if (!current->thread.regs) {
|
2006-01-12 09:06:02 +00:00
|
|
|
struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE;
|
|
|
|
|
current->thread.regs = regs - 1;
|
2005-10-10 12:29:05 +00:00
|
|
|
}
|
|
|
|
|
|
2005-09-26 06:04:21 +00:00
|
|
|
memset(regs->gpr, 0, sizeof(regs->gpr));
|
|
|
|
|
regs->ctr = 0;
|
|
|
|
|
regs->link = 0;
|
|
|
|
|
regs->xer = 0;
|
|
|
|
|
regs->ccr = 0;
|
|
|
|
|
regs->gpr[1] = sp;
|
2005-10-10 12:29:05 +00:00
|
|
|
|
2007-09-24 23:52:44 +00:00
|
|
|
/*
|
|
|
|
|
* We have just cleared all the nonvolatile GPRs, so make
|
|
|
|
|
* FULL_REGS(regs) return true. This is necessary to allow
|
|
|
|
|
* ptrace to examine the thread immediately after exec.
|
|
|
|
|
*/
|
|
|
|
|
regs->trap &= ~1UL;
|
|
|
|
|
|
2005-10-10 12:29:05 +00:00
|
|
|
#ifdef CONFIG_PPC32
|
|
|
|
|
regs->mq = 0;
|
|
|
|
|
regs->nip = start;
|
2005-09-26 06:04:21 +00:00
|
|
|
regs->msr = MSR_USER;
|
2005-10-10 12:29:05 +00:00
|
|
|
#else
|
2010-07-29 22:04:39 +00:00
|
|
|
if (!is_32bit_task()) {
|
2005-10-21 06:01:33 +00:00
|
|
|
unsigned long entry, toc;
|
2005-10-10 12:29:05 +00:00
|
|
|
|
|
|
|
|
/* start is a relocated pointer to the function descriptor for
|
|
|
|
|
* the elf _start routine. The first entry in the function
|
|
|
|
|
* descriptor is the entry address of _start and the second
|
|
|
|
|
* entry is the TOC value we need to use.
|
|
|
|
|
*/
|
|
|
|
|
__get_user(entry, (unsigned long __user *)start);
|
|
|
|
|
__get_user(toc, (unsigned long __user *)start+1);
|
|
|
|
|
|
|
|
|
|
/* Check whether the e_entry function descriptor entries
|
|
|
|
|
* need to be relocated before we can use them.
|
|
|
|
|
*/
|
|
|
|
|
if (load_addr != 0) {
|
|
|
|
|
entry += load_addr;
|
|
|
|
|
toc += load_addr;
|
|
|
|
|
}
|
|
|
|
|
regs->nip = entry;
|
|
|
|
|
regs->gpr[2] = toc;
|
|
|
|
|
regs->msr = MSR_USER64;
|
2005-10-13 03:40:54 +00:00
|
|
|
} else {
|
|
|
|
|
regs->nip = start;
|
|
|
|
|
regs->gpr[2] = 0;
|
|
|
|
|
regs->msr = MSR_USER32;
|
2005-10-10 12:29:05 +00:00
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
2005-11-30 02:20:54 +00:00
|
|
|
discard_lazy_cpu_state();
|
2008-06-25 04:07:18 +00:00
|
|
|
#ifdef CONFIG_VSX
|
|
|
|
|
current->thread.used_vsr = 0;
|
|
|
|
|
#endif
|
2005-09-26 06:04:21 +00:00
|
|
|
memset(current->thread.fpr, 0, sizeof(current->thread.fpr));
|
[PATCH] powerpc: Fix handling of fpscr on 64-bit
The recent merge of fpu.S broken the handling of fpscr for
ARCH=powerpc and CONFIG_PPC64=y. FP registers could be corrupted,
leading to strange random application crashes.
The confusion arises, because the thread_struct has (and requires) a
64-bit area to save the fpscr, because we use load/store double
instructions to get it in to/out of the FPU. However, only the low
32-bits are actually used, so we want to treat it as a 32-bit quantity
when manipulating its bits to avoid extra load/stores on 32-bit. This
patch replaces the current definition with a structure of two 32-bit
quantities (pad and val), to clarify things as much as is possible.
The 'val' field is used when manipulating bits, the structure itself
is used when obtaining the address for loading/unloading the value
from the FPU.
While we're at it, consolidate the 4 (!) almost identical versions of
cvt_fd() and cvt_df() (arch/ppc/kernel/misc.S,
arch/ppc64/kernel/misc.S, arch/powerpc/kernel/misc_32.S,
arch/powerpc/kernel/misc_64.S) into a single version in fpu.S. The
new version takes a pointer to thread_struct and applies the correct
offset itself, rather than a pointer to the fpscr field itself, again
to avoid confusion as to which is the correct field to use.
Finally, this patch makes ARCH=ppc64 also use the consolidated fpu.S
code, which it previously did not.
Built for G5 (ARCH=ppc64 and ARCH=powerpc), 32-bit powermac (ARCH=ppc
and ARCH=powerpc) and Walnut (ARCH=ppc, CONFIG_MATH_EMULATION=y).
Booted on G5 (ARCH=powerpc) and things which previously fell over no
longer do.
Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-10-27 06:27:25 +00:00
|
|
|
current->thread.fpscr.val = 0;
|
2005-09-26 06:04:21 +00:00
|
|
|
#ifdef CONFIG_ALTIVEC
|
|
|
|
|
memset(current->thread.vr, 0, sizeof(current->thread.vr));
|
|
|
|
|
memset(¤t->thread.vscr, 0, sizeof(current->thread.vscr));
|
2005-10-10 12:29:05 +00:00
|
|
|
current->thread.vscr.u[3] = 0x00010000; /* Java mode disabled */
|
2005-09-26 06:04:21 +00:00
|
|
|
current->thread.vrsave = 0;
|
|
|
|
|
current->thread.used_vr = 0;
|
|
|
|
|
#endif /* CONFIG_ALTIVEC */
|
|
|
|
|
#ifdef CONFIG_SPE
|
|
|
|
|
memset(current->thread.evr, 0, sizeof(current->thread.evr));
|
|
|
|
|
current->thread.acc = 0;
|
|
|
|
|
current->thread.spefscr = 0;
|
|
|
|
|
current->thread.used_spe = 0;
|
|
|
|
|
#endif /* CONFIG_SPE */
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
|
|
|
|
|
| PR_FP_EXC_RES | PR_FP_EXC_INV)
|
|
|
|
|
|
|
|
|
|
int set_fpexc_mode(struct task_struct *tsk, unsigned int val)
|
|
|
|
|
{
|
|
|
|
|
struct pt_regs *regs = tsk->thread.regs;
|
|
|
|
|
|
|
|
|
|
/* This is a bit hairy. If we are an SPE enabled processor
|
|
|
|
|
* (have embedded fp) we store the IEEE exception enable flags in
|
|
|
|
|
* fpexc_mode. fpexc_mode is also used for setting FP exception
|
|
|
|
|
* mode (asyn, precise, disabled) for 'Classic' FP. */
|
|
|
|
|
if (val & PR_FP_EXC_SW_ENABLE) {
|
|
|
|
|
#ifdef CONFIG_SPE
|
2007-09-13 06:44:20 +00:00
|
|
|
if (cpu_has_feature(CPU_FTR_SPE)) {
|
|
|
|
|
tsk->thread.fpexc_mode = val &
|
|
|
|
|
(PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT);
|
|
|
|
|
return 0;
|
|
|
|
|
} else {
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
2005-09-26 06:04:21 +00:00
|
|
|
#else
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
#endif
|
|
|
|
|
}
|
2005-10-10 12:29:05 +00:00
|
|
|
|
|
|
|
|
/* on a CONFIG_SPE this does not hurt us. The bits that
|
|
|
|
|
* __pack_fe01 use do not overlap with bits used for
|
|
|
|
|
* PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits
|
|
|
|
|
* on CONFIG_SPE implementations are reserved so writing to
|
|
|
|
|
* them does not change anything */
|
|
|
|
|
if (val > PR_FP_EXC_PRECISE)
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
tsk->thread.fpexc_mode = __pack_fe01(val);
|
|
|
|
|
if (regs != NULL && (regs->msr & MSR_FP) != 0)
|
|
|
|
|
regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1))
|
|
|
|
|
| tsk->thread.fpexc_mode;
|
2005-09-26 06:04:21 +00:00
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int get_fpexc_mode(struct task_struct *tsk, unsigned long adr)
|
|
|
|
|
{
|
|
|
|
|
unsigned int val;
|
|
|
|
|
|
|
|
|
|
if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE)
|
|
|
|
|
#ifdef CONFIG_SPE
|
2007-09-13 06:44:20 +00:00
|
|
|
if (cpu_has_feature(CPU_FTR_SPE))
|
|
|
|
|
val = tsk->thread.fpexc_mode;
|
|
|
|
|
else
|
|
|
|
|
return -EINVAL;
|
2005-09-26 06:04:21 +00:00
|
|
|
#else
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
#endif
|
|
|
|
|
else
|
|
|
|
|
val = __unpack_fe01(tsk->thread.fpexc_mode);
|
|
|
|
|
return put_user(val, (unsigned int __user *) adr);
|
|
|
|
|
}
|
|
|
|
|
|
2006-06-07 06:14:40 +00:00
|
|
|
int set_endian(struct task_struct *tsk, unsigned int val)
|
|
|
|
|
{
|
|
|
|
|
struct pt_regs *regs = tsk->thread.regs;
|
|
|
|
|
|
|
|
|
|
if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) ||
|
|
|
|
|
(val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE)))
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
|
|
if (regs == NULL)
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
|
|
if (val == PR_ENDIAN_BIG)
|
|
|
|
|
regs->msr &= ~MSR_LE;
|
|
|
|
|
else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE)
|
|
|
|
|
regs->msr |= MSR_LE;
|
|
|
|
|
else
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int get_endian(struct task_struct *tsk, unsigned long adr)
|
|
|
|
|
{
|
|
|
|
|
struct pt_regs *regs = tsk->thread.regs;
|
|
|
|
|
unsigned int val;
|
|
|
|
|
|
|
|
|
|
if (!cpu_has_feature(CPU_FTR_PPC_LE) &&
|
|
|
|
|
!cpu_has_feature(CPU_FTR_REAL_LE))
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
|
|
if (regs == NULL)
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
|
|
if (regs->msr & MSR_LE) {
|
|
|
|
|
if (cpu_has_feature(CPU_FTR_REAL_LE))
|
|
|
|
|
val = PR_ENDIAN_LITTLE;
|
|
|
|
|
else
|
|
|
|
|
val = PR_ENDIAN_PPC_LITTLE;
|
|
|
|
|
} else
|
|
|
|
|
val = PR_ENDIAN_BIG;
|
|
|
|
|
|
|
|
|
|
return put_user(val, (unsigned int __user *)adr);
|
|
|
|
|
}
|
|
|
|
|
|
2006-06-07 06:15:39 +00:00
|
|
|
int set_unalign_ctl(struct task_struct *tsk, unsigned int val)
|
|
|
|
|
{
|
|
|
|
|
tsk->thread.align_ctl = val;
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int get_unalign_ctl(struct task_struct *tsk, unsigned long adr)
|
|
|
|
|
{
|
|
|
|
|
return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr);
|
|
|
|
|
}
|
|
|
|
|
|
2005-10-10 12:29:05 +00:00
|
|
|
#define TRUNC_PTR(x) ((typeof(x))(((unsigned long)(x)) & 0xffffffff))
|
|
|
|
|
|
2005-09-26 06:04:21 +00:00
|
|
|
int sys_clone(unsigned long clone_flags, unsigned long usp,
|
|
|
|
|
int __user *parent_tidp, void __user *child_threadptr,
|
|
|
|
|
int __user *child_tidp, int p6,
|
|
|
|
|
struct pt_regs *regs)
|
|
|
|
|
{
|
|
|
|
|
CHECK_FULL_REGS(regs);
|
|
|
|
|
if (usp == 0)
|
|
|
|
|
usp = regs->gpr[1]; /* stack pointer for child */
|
2005-10-10 12:29:05 +00:00
|
|
|
#ifdef CONFIG_PPC64
|
2010-07-29 22:04:39 +00:00
|
|
|
if (is_32bit_task()) {
|
2005-10-10 12:29:05 +00:00
|
|
|
parent_tidp = TRUNC_PTR(parent_tidp);
|
|
|
|
|
child_tidp = TRUNC_PTR(child_tidp);
|
|
|
|
|
}
|
|
|
|
|
#endif
|
2005-09-26 06:04:21 +00:00
|
|
|
return do_fork(clone_flags, usp, regs, 0, parent_tidp, child_tidp);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int sys_fork(unsigned long p1, unsigned long p2, unsigned long p3,
|
|
|
|
|
unsigned long p4, unsigned long p5, unsigned long p6,
|
|
|
|
|
struct pt_regs *regs)
|
|
|
|
|
{
|
|
|
|
|
CHECK_FULL_REGS(regs);
|
|
|
|
|
return do_fork(SIGCHLD, regs->gpr[1], regs, 0, NULL, NULL);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int sys_vfork(unsigned long p1, unsigned long p2, unsigned long p3,
|
|
|
|
|
unsigned long p4, unsigned long p5, unsigned long p6,
|
|
|
|
|
struct pt_regs *regs)
|
|
|
|
|
{
|
|
|
|
|
CHECK_FULL_REGS(regs);
|
|
|
|
|
return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->gpr[1],
|
|
|
|
|
regs, 0, NULL, NULL);
|
|
|
|
|
}
|
|
|
|
|
|
2012-08-31 19:48:05 +00:00
|
|
|
void __ret_from_kernel_execve(struct pt_regs *normal)
|
|
|
|
|
__noreturn;
|
|
|
|
|
|
|
|
|
|
void ret_from_kernel_execve(struct pt_regs *normal)
|
2005-09-26 06:04:21 +00:00
|
|
|
{
|
2012-08-31 19:48:05 +00:00
|
|
|
set_thread_flag(TIF_RESTOREALL);
|
|
|
|
|
__ret_from_kernel_execve(normal);
|
2005-09-26 06:04:21 +00:00
|
|
|
}
|
|
|
|
|
|
2007-02-19 00:42:42 +00:00
|
|
|
static inline int valid_irq_stack(unsigned long sp, struct task_struct *p,
|
|
|
|
|
unsigned long nbytes)
|
|
|
|
|
{
|
|
|
|
|
unsigned long stack_page;
|
|
|
|
|
unsigned long cpu = task_cpu(p);
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Avoid crashing if the stack has overflowed and corrupted
|
|
|
|
|
* task_cpu(p), which is in the thread_info struct.
|
|
|
|
|
*/
|
|
|
|
|
if (cpu < NR_CPUS && cpu_possible(cpu)) {
|
|
|
|
|
stack_page = (unsigned long) hardirq_ctx[cpu];
|
|
|
|
|
if (sp >= stack_page + sizeof(struct thread_struct)
|
|
|
|
|
&& sp <= stack_page + THREAD_SIZE - nbytes)
|
|
|
|
|
return 1;
|
|
|
|
|
|
|
|
|
|
stack_page = (unsigned long) softirq_ctx[cpu];
|
|
|
|
|
if (sp >= stack_page + sizeof(struct thread_struct)
|
|
|
|
|
&& sp <= stack_page + THREAD_SIZE - nbytes)
|
|
|
|
|
return 1;
|
|
|
|
|
}
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2006-03-27 00:46:18 +00:00
|
|
|
int validate_sp(unsigned long sp, struct task_struct *p,
|
2005-09-26 06:04:21 +00:00
|
|
|
unsigned long nbytes)
|
|
|
|
|
{
|
2006-01-12 09:06:02 +00:00
|
|
|
unsigned long stack_page = (unsigned long)task_stack_page(p);
|
2005-09-26 06:04:21 +00:00
|
|
|
|
|
|
|
|
if (sp >= stack_page + sizeof(struct thread_struct)
|
|
|
|
|
&& sp <= stack_page + THREAD_SIZE - nbytes)
|
|
|
|
|
return 1;
|
|
|
|
|
|
2007-02-19 00:42:42 +00:00
|
|
|
return valid_irq_stack(sp, p, nbytes);
|
2005-09-26 06:04:21 +00:00
|
|
|
}
|
|
|
|
|
|
2006-03-27 00:46:18 +00:00
|
|
|
EXPORT_SYMBOL(validate_sp);
|
|
|
|
|
|
2005-09-26 06:04:21 +00:00
|
|
|
unsigned long get_wchan(struct task_struct *p)
|
|
|
|
|
{
|
|
|
|
|
unsigned long ip, sp;
|
|
|
|
|
int count = 0;
|
|
|
|
|
|
|
|
|
|
if (!p || p == current || p->state == TASK_RUNNING)
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
sp = p->thread.ksp;
|
2008-04-17 04:34:59 +00:00
|
|
|
if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
|
2005-09-26 06:04:21 +00:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
do {
|
|
|
|
|
sp = *(unsigned long *)sp;
|
2008-04-17 04:34:59 +00:00
|
|
|
if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
|
2005-09-26 06:04:21 +00:00
|
|
|
return 0;
|
|
|
|
|
if (count > 0) {
|
2008-04-17 04:34:59 +00:00
|
|
|
ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE];
|
2005-09-26 06:04:21 +00:00
|
|
|
if (!in_sched_functions(ip))
|
|
|
|
|
return ip;
|
|
|
|
|
}
|
|
|
|
|
} while (count++ < 16);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
2005-10-10 12:29:05 +00:00
|
|
|
|
2008-11-20 03:24:07 +00:00
|
|
|
static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH;
|
2005-10-10 12:29:05 +00:00
|
|
|
|
|
|
|
|
void show_stack(struct task_struct *tsk, unsigned long *stack)
|
|
|
|
|
{
|
|
|
|
|
unsigned long sp, ip, lr, newsp;
|
|
|
|
|
int count = 0;
|
|
|
|
|
int firstframe = 1;
|
2009-02-10 05:10:27 +00:00
|
|
|
#ifdef CONFIG_FUNCTION_GRAPH_TRACER
|
|
|
|
|
int curr_frame = current->curr_ret_stack;
|
|
|
|
|
extern void return_to_handler(void);
|
2009-09-15 15:20:15 +00:00
|
|
|
unsigned long rth = (unsigned long)return_to_handler;
|
|
|
|
|
unsigned long mrth = -1;
|
2009-02-10 05:10:27 +00:00
|
|
|
#ifdef CONFIG_PPC64
|
2009-09-15 15:20:15 +00:00
|
|
|
extern void mod_return_to_handler(void);
|
|
|
|
|
rth = *(unsigned long *)rth;
|
|
|
|
|
mrth = (unsigned long)mod_return_to_handler;
|
|
|
|
|
mrth = *(unsigned long *)mrth;
|
2009-02-10 05:10:27 +00:00
|
|
|
#endif
|
|
|
|
|
#endif
|
2005-10-10 12:29:05 +00:00
|
|
|
|
|
|
|
|
sp = (unsigned long) stack;
|
|
|
|
|
if (tsk == NULL)
|
|
|
|
|
tsk = current;
|
|
|
|
|
if (sp == 0) {
|
|
|
|
|
if (tsk == current)
|
|
|
|
|
asm("mr %0,1" : "=r" (sp));
|
|
|
|
|
else
|
|
|
|
|
sp = tsk->thread.ksp;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
lr = 0;
|
|
|
|
|
printk("Call Trace:\n");
|
|
|
|
|
do {
|
2008-04-17 04:34:59 +00:00
|
|
|
if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD))
|
2005-10-10 12:29:05 +00:00
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
stack = (unsigned long *) sp;
|
|
|
|
|
newsp = stack[0];
|
2008-04-17 04:34:59 +00:00
|
|
|
ip = stack[STACK_FRAME_LR_SAVE];
|
2005-10-10 12:29:05 +00:00
|
|
|
if (!firstframe || ip != lr) {
|
2008-07-07 03:44:31 +00:00
|
|
|
printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip);
|
2009-02-10 05:10:27 +00:00
|
|
|
#ifdef CONFIG_FUNCTION_GRAPH_TRACER
|
2009-09-15 15:20:15 +00:00
|
|
|
if ((ip == rth || ip == mrth) && curr_frame >= 0) {
|
2009-02-10 05:10:27 +00:00
|
|
|
printk(" (%pS)",
|
|
|
|
|
(void *)current->ret_stack[curr_frame].ret);
|
|
|
|
|
curr_frame--;
|
|
|
|
|
}
|
|
|
|
|
#endif
|
2005-10-10 12:29:05 +00:00
|
|
|
if (firstframe)
|
|
|
|
|
printk(" (unreliable)");
|
|
|
|
|
printk("\n");
|
|
|
|
|
}
|
|
|
|
|
firstframe = 0;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* See if this is an exception frame.
|
|
|
|
|
* We look for the "regshere" marker in the current frame.
|
|
|
|
|
*/
|
2008-04-17 04:34:59 +00:00
|
|
|
if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE)
|
|
|
|
|
&& stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) {
|
2005-10-10 12:29:05 +00:00
|
|
|
struct pt_regs *regs = (struct pt_regs *)
|
|
|
|
|
(sp + STACK_FRAME_OVERHEAD);
|
|
|
|
|
lr = regs->link;
|
2008-07-07 03:44:31 +00:00
|
|
|
printk("--- Exception: %lx at %pS\n LR = %pS\n",
|
|
|
|
|
regs->trap, (void *)regs->nip, (void *)lr);
|
2005-10-10 12:29:05 +00:00
|
|
|
firstframe = 1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
sp = newsp;
|
|
|
|
|
} while (count++ < kstack_depth_to_print);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void dump_stack(void)
|
|
|
|
|
{
|
|
|
|
|
show_stack(current, NULL);
|
|
|
|
|
}
|
|
|
|
|
EXPORT_SYMBOL(dump_stack);
|
2006-02-13 03:48:35 +00:00
|
|
|
|
|
|
|
|
#ifdef CONFIG_PPC64
|
2012-03-01 01:45:27 +00:00
|
|
|
/* Called with hard IRQs off */
|
|
|
|
|
void __ppc64_runlatch_on(void)
|
2006-02-13 03:48:35 +00:00
|
|
|
{
|
2012-03-01 01:45:27 +00:00
|
|
|
struct thread_info *ti = current_thread_info();
|
2006-02-13 03:48:35 +00:00
|
|
|
unsigned long ctrl;
|
|
|
|
|
|
2012-03-01 01:45:27 +00:00
|
|
|
ctrl = mfspr(SPRN_CTRLF);
|
|
|
|
|
ctrl |= CTRL_RUNLATCH;
|
|
|
|
|
mtspr(SPRN_CTRLT, ctrl);
|
2006-02-13 03:48:35 +00:00
|
|
|
|
2012-04-11 00:42:15 +00:00
|
|
|
ti->local_flags |= _TLF_RUNLATCH;
|
2006-02-13 03:48:35 +00:00
|
|
|
}
|
|
|
|
|
|
2012-03-01 01:45:27 +00:00
|
|
|
/* Called with hard IRQs off */
|
2010-08-06 03:28:19 +00:00
|
|
|
void __ppc64_runlatch_off(void)
|
2006-02-13 03:48:35 +00:00
|
|
|
{
|
2012-03-01 01:45:27 +00:00
|
|
|
struct thread_info *ti = current_thread_info();
|
2006-02-13 03:48:35 +00:00
|
|
|
unsigned long ctrl;
|
|
|
|
|
|
2012-04-11 00:42:15 +00:00
|
|
|
ti->local_flags &= ~_TLF_RUNLATCH;
|
2006-02-13 03:48:35 +00:00
|
|
|
|
2010-08-06 03:28:19 +00:00
|
|
|
ctrl = mfspr(SPRN_CTRLF);
|
|
|
|
|
ctrl &= ~CTRL_RUNLATCH;
|
|
|
|
|
mtspr(SPRN_CTRLT, ctrl);
|
2006-02-13 03:48:35 +00:00
|
|
|
}
|
2012-03-01 01:45:27 +00:00
|
|
|
#endif /* CONFIG_PPC64 */
|
2008-04-18 06:56:17 +00:00
|
|
|
|
2009-02-22 01:50:03 +00:00
|
|
|
unsigned long arch_align_stack(unsigned long sp)
|
|
|
|
|
{
|
|
|
|
|
if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
|
|
|
|
|
sp -= get_random_int() & ~PAGE_MASK;
|
|
|
|
|
return sp & ~0xf;
|
|
|
|
|
}
|
2009-02-22 01:50:04 +00:00
|
|
|
|
|
|
|
|
static inline unsigned long brk_rnd(void)
|
|
|
|
|
{
|
|
|
|
|
unsigned long rnd = 0;
|
|
|
|
|
|
|
|
|
|
/* 8MB for 32bit, 1GB for 64bit */
|
|
|
|
|
if (is_32bit_task())
|
|
|
|
|
rnd = (long)(get_random_int() % (1<<(23-PAGE_SHIFT)));
|
|
|
|
|
else
|
|
|
|
|
rnd = (long)(get_random_int() % (1<<(30-PAGE_SHIFT)));
|
|
|
|
|
|
|
|
|
|
return rnd << PAGE_SHIFT;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
unsigned long arch_randomize_brk(struct mm_struct *mm)
|
|
|
|
|
{
|
2009-09-21 16:52:35 +00:00
|
|
|
unsigned long base = mm->brk;
|
|
|
|
|
unsigned long ret;
|
|
|
|
|
|
2009-10-16 07:05:17 +00:00
|
|
|
#ifdef CONFIG_PPC_STD_MMU_64
|
2009-09-21 16:52:35 +00:00
|
|
|
/*
|
|
|
|
|
* If we are using 1TB segments and we are allowed to randomise
|
|
|
|
|
* the heap, we can put it above 1TB so it is backed by a 1TB
|
|
|
|
|
* segment. Otherwise the heap will be in the bottom 1TB
|
|
|
|
|
* which always uses 256MB segments and this may result in a
|
|
|
|
|
* performance penalty.
|
|
|
|
|
*/
|
|
|
|
|
if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T))
|
|
|
|
|
base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T);
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
ret = PAGE_ALIGN(base + brk_rnd());
|
2009-02-22 01:50:04 +00:00
|
|
|
|
|
|
|
|
if (ret < mm->brk)
|
|
|
|
|
return mm->brk;
|
|
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
2009-02-22 01:50:07 +00:00
|
|
|
|
|
|
|
|
unsigned long randomize_et_dyn(unsigned long base)
|
|
|
|
|
{
|
|
|
|
|
unsigned long ret = PAGE_ALIGN(base + brk_rnd());
|
|
|
|
|
|
|
|
|
|
if (ret < base)
|
|
|
|
|
return base;
|
|
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
}
|