2005-04-16 22:20:36 +00:00
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#ifndef _ASM_M32R_SIGCONTEXT_H
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#define _ASM_M32R_SIGCONTEXT_H
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/* $Id$ */
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struct sigcontext {
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/* CPU registers */
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/* Saved main processor registers. */
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unsigned long sc_r4;
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unsigned long sc_r5;
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unsigned long sc_r6;
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struct pt_regs *sc_pt_regs;
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unsigned long sc_r0;
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unsigned long sc_r1;
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unsigned long sc_r2;
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unsigned long sc_r3;
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unsigned long sc_r7;
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unsigned long sc_r8;
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unsigned long sc_r9;
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unsigned long sc_r10;
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unsigned long sc_r11;
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unsigned long sc_r12;
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/* Saved main processor status and miscellaneous context registers. */
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#if defined(CONFIG_ISA_M32R2) && defined(CONFIG_ISA_DSP_LEVEL2)
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unsigned long sc_acc0h;
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unsigned long sc_acc0l;
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unsigned long sc_acc1h;
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unsigned long sc_acc1l;
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#elif defined(CONFIG_ISA_M32R2) || defined(CONFIG_ISA_M32R)
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unsigned long sc_acch;
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unsigned long sc_accl;
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[PATCH] m32r: Fix pt_regs for !COFNIG_ISA_DSP_LEVEL2 target
This modification is required to fix debugging function for m32r targets
with !CONFIG_ISA_DSP_LEVEL2, by unifying 'struct pt_regs' and 'struct
sigcontext' size for all M32R ISA.
Some m32r processor core with !CONFIG_ISA_DSP_LEVEL2 configuration has only
single accumulator a0 (ex. VDEC2 core, M32102 core, etc.), the others with
CONFIG_ISA_DSP_LEVEL2 has two accumulators, a0 and a1.
This means there are two variations of thread context. So far, we reduced
and changed stackframe size at a syscall for their context size. However,
this causes a problem that a GDB for processors with CONFIG_ISA_DSP_LEVEL2
cannot be used for processors with !CONFIG_ISA_DSP_LEVEL2.
From the viewpoint of GDB support, we should reduce such variation of
stackframe size for simplicity.
In this patch, dummy members are added to 'struct pt_regs' and 'struct
sigcontext' to adjust their size for !CONFIG_ISA_DSP_LEVEL2.
This modification is also a one step for a GDB update in future.
Currently, on the m32r, GDB can access process's context by using ptrace
functions in a simple way of register by register access. By unifying
stackframe size, we have a possibility to make use of ptrace functions of
not only a single register access but also block register access,
PTRACE_{GETREGS,PUTREGS}.
However, for this purpose, we might have to modify stackframe structure
some more; for example, PSW (processor status word) register should be
pre-processed before pushing to stack at a syscall, and so on. In this
case, we must update carefully both kernel and GDB at a time...
Signed-off-by: Hayato Fujiwara <fujiwara@linux-m32r.org>
Signed-off-by: Hirokazu Takata <takata@linux-m32r.org>
Cc: Kei Sakamoto <ksakamot@linux-m32r.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-04-19 05:21:20 +00:00
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unsigned long sc_dummy_acc1h;
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unsigned long sc_dummy_acc1l;
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2005-04-16 22:20:36 +00:00
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#else
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#error unknown isa configuration
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#endif
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unsigned long sc_psw;
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unsigned long sc_bpc; /* saved PC for TRAP syscalls */
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unsigned long sc_bbpsw;
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unsigned long sc_bbpc;
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unsigned long sc_spu; /* saved user stack */
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unsigned long sc_fp;
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unsigned long sc_lr; /* saved PC for JL syscalls */
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unsigned long sc_spi; /* saved kernel stack */
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unsigned long oldmask;
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};
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#endif /* _ASM_M32R_SIGCONTEXT_H */
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