215 lines
5.6 KiB
C
215 lines
5.6 KiB
C
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Time operations for IP22 machines. Original code may come from
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* Ralf Baechle or David S. Miller (sorry guys, i'm really not sure)
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*
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* Copyright (C) 2001 by Ladislav Michl
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* Copyright (C) 2003 Ralf Baechle (ralf@linux-mips.org)
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*/
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#include <linux/bcd.h>
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#include <linux/ds1286.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/kernel_stat.h>
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#include <linux/time.h>
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#include <asm/cpu.h>
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#include <asm/mipsregs.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/time.h>
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#include <asm/sgialib.h>
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#include <asm/sgi/ioc.h>
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#include <asm/sgi/hpc3.h>
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#include <asm/sgi/ip22.h>
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/*
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* note that mktime uses month from 1 to 12 while to_tm
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* uses 0 to 11.
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*/
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static unsigned long indy_rtc_get_time(void)
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{
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unsigned int yrs, mon, day, hrs, min, sec;
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unsigned int save_control;
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save_control = hpc3c0->rtcregs[RTC_CMD] & 0xff;
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hpc3c0->rtcregs[RTC_CMD] = save_control | RTC_TE;
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sec = BCD2BIN(hpc3c0->rtcregs[RTC_SECONDS] & 0xff);
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min = BCD2BIN(hpc3c0->rtcregs[RTC_MINUTES] & 0xff);
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hrs = BCD2BIN(hpc3c0->rtcregs[RTC_HOURS] & 0x3f);
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day = BCD2BIN(hpc3c0->rtcregs[RTC_DATE] & 0xff);
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mon = BCD2BIN(hpc3c0->rtcregs[RTC_MONTH] & 0x1f);
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yrs = BCD2BIN(hpc3c0->rtcregs[RTC_YEAR] & 0xff);
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hpc3c0->rtcregs[RTC_CMD] = save_control;
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if (yrs < 45)
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yrs += 30;
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if ((yrs += 40) < 70)
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yrs += 100;
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return mktime(yrs + 1900, mon, day, hrs, min, sec);
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}
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static int indy_rtc_set_time(unsigned long tim)
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{
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struct rtc_time tm;
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unsigned int save_control;
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to_tm(tim, &tm);
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tm.tm_mon += 1; /* tm_mon starts at zero */
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tm.tm_year -= 1940;
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if (tm.tm_year >= 100)
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tm.tm_year -= 100;
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save_control = hpc3c0->rtcregs[RTC_CMD] & 0xff;
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hpc3c0->rtcregs[RTC_CMD] = save_control | RTC_TE;
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hpc3c0->rtcregs[RTC_YEAR] = BIN2BCD(tm.tm_sec);
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hpc3c0->rtcregs[RTC_MONTH] = BIN2BCD(tm.tm_mon);
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hpc3c0->rtcregs[RTC_DATE] = BIN2BCD(tm.tm_mday);
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hpc3c0->rtcregs[RTC_HOURS] = BIN2BCD(tm.tm_hour);
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hpc3c0->rtcregs[RTC_MINUTES] = BIN2BCD(tm.tm_min);
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hpc3c0->rtcregs[RTC_SECONDS] = BIN2BCD(tm.tm_sec);
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hpc3c0->rtcregs[RTC_HUNDREDTH_SECOND] = 0;
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hpc3c0->rtcregs[RTC_CMD] = save_control;
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return 0;
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}
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static unsigned long dosample(void)
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{
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u32 ct0, ct1;
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volatile u8 msb, lsb;
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/* Start the counter. */
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sgint->tcword = (SGINT_TCWORD_CNT2 | SGINT_TCWORD_CALL |
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SGINT_TCWORD_MRGEN);
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sgint->tcnt2 = SGINT_TCSAMP_COUNTER & 0xff;
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sgint->tcnt2 = SGINT_TCSAMP_COUNTER >> 8;
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/* Get initial counter invariant */
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ct0 = read_c0_count();
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/* Latch and spin until top byte of counter2 is zero */
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do {
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sgint->tcword = SGINT_TCWORD_CNT2 | SGINT_TCWORD_CLAT;
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lsb = sgint->tcnt2;
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msb = sgint->tcnt2;
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ct1 = read_c0_count();
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} while (msb);
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/* Stop the counter. */
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sgint->tcword = (SGINT_TCWORD_CNT2 | SGINT_TCWORD_CALL |
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SGINT_TCWORD_MSWST);
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/*
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* Return the difference, this is how far the r4k counter increments
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* for every 1/HZ seconds. We round off the nearest 1 MHz of master
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* clock (= 1000000 / HZ / 2).
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*/
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/*return (ct1 - ct0 + (500000/HZ/2)) / (500000/HZ) * (500000/HZ);*/
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return (ct1 - ct0) / (500000/HZ) * (500000/HZ);
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}
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/*
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* Here we need to calibrate the cycle counter to at least be close.
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*/
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static __init void indy_time_init(void)
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{
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unsigned long r4k_ticks[3];
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unsigned long r4k_tick;
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/*
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* Figure out the r4k offset, the algorithm is very simple and works in
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* _all_ cases as long as the 8254 counter register itself works ok (as
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* an interrupt driving timer it does not because of bug, this is why
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* we are using the onchip r4k counter/compare register to serve this
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* purpose, but for r4k_offset calculation it will work ok for us).
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* There are other very complicated ways of performing this calculation
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* but this one works just fine so I am not going to futz around. ;-)
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*/
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printk(KERN_INFO "Calibrating system timer... ");
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dosample(); /* Prime cache. */
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dosample(); /* Prime cache. */
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/* Zero is NOT an option. */
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do {
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r4k_ticks[0] = dosample();
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} while (!r4k_ticks[0]);
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do {
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r4k_ticks[1] = dosample();
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} while (!r4k_ticks[1]);
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if (r4k_ticks[0] != r4k_ticks[1]) {
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printk("warning: timer counts differ, retrying... ");
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r4k_ticks[2] = dosample();
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if (r4k_ticks[2] == r4k_ticks[0]
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|| r4k_ticks[2] == r4k_ticks[1])
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r4k_tick = r4k_ticks[2];
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else {
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printk("disagreement, using average... ");
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r4k_tick = (r4k_ticks[0] + r4k_ticks[1]
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+ r4k_ticks[2]) / 3;
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}
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} else
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r4k_tick = r4k_ticks[0];
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printk("%d [%d.%04d MHz CPU]\n", (int) r4k_tick,
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(int) (r4k_tick / (500000 / HZ)),
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(int) (r4k_tick % (500000 / HZ)));
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mips_hpt_frequency = r4k_tick * HZ;
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}
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/* Generic SGI handler for (spurious) 8254 interrupts */
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void indy_8254timer_irq(struct pt_regs *regs)
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{
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int irq = SGI_8254_0_IRQ;
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ULONG cnt;
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char c;
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irq_enter();
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kstat_this_cpu.irqs[irq]++;
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printk(KERN_ALERT "Oops, got 8254 interrupt.\n");
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ArcRead(0, &c, 1, &cnt);
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ArcEnterInteractiveMode();
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irq_exit();
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}
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void indy_r4k_timer_interrupt(struct pt_regs *regs)
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{
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int irq = SGI_TIMER_IRQ;
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irq_enter();
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kstat_this_cpu.irqs[irq]++;
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timer_interrupt(irq, NULL, regs);
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irq_exit();
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}
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extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
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static void indy_timer_setup(struct irqaction *irq)
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{
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/* over-write the handler, we use our own way */
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irq->handler = no_action;
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/* setup irqaction */
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setup_irq(SGI_TIMER_IRQ, irq);
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}
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void __init ip22_time_init(void)
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{
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/* setup hookup functions */
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rtc_get_time = indy_rtc_get_time;
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rtc_set_time = indy_rtc_set_time;
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board_time_init = indy_time_init;
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board_timer_setup = indy_timer_setup;
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}
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