239 lines
6.3 KiB
C
239 lines
6.3 KiB
C
![]() |
/*
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* drivers/mtd/nand/ams-delta.c
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*
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* Copyright (C) 2006 Jonathan McDowell <noodles@earth.li>
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*
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* Derived from drivers/mtd/toto.c
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Overview:
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* This is a device driver for the NAND flash device found on the
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* Amstrad E3 (Delta).
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*/
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#include <linux/slab.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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#include <asm/sizes.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/board-ams-delta.h>
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/*
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* MTD structure for E3 (Delta)
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*/
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static struct mtd_info *ams_delta_mtd = NULL;
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#define NAND_MASK (AMS_DELTA_LATCH2_NAND_NRE | AMS_DELTA_LATCH2_NAND_NWE | AMS_DELTA_LATCH2_NAND_CLE | AMS_DELTA_LATCH2_NAND_ALE | AMS_DELTA_LATCH2_NAND_NCE | AMS_DELTA_LATCH2_NAND_NWP)
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#define T_NAND_CTL_CLRALE(iob) ams_delta_latch2_write(AMS_DELTA_LATCH2_NAND_ALE, 0)
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#define T_NAND_CTL_SETALE(iob) ams_delta_latch2_write(AMS_DELTA_LATCH2_NAND_ALE, AMS_DELTA_LATCH2_NAND_ALE)
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#define T_NAND_CTL_CLRCLE(iob) ams_delta_latch2_write(AMS_DELTA_LATCH2_NAND_CLE, 0)
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#define T_NAND_CTL_SETCLE(iob) ams_delta_latch2_write(AMS_DELTA_LATCH2_NAND_CLE, AMS_DELTA_LATCH2_NAND_CLE)
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#define T_NAND_CTL_SETNCE(iob) ams_delta_latch2_write(AMS_DELTA_LATCH2_NAND_NCE, 0)
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#define T_NAND_CTL_CLRNCE(iob) ams_delta_latch2_write(AMS_DELTA_LATCH2_NAND_NCE, AMS_DELTA_LATCH2_NAND_NCE)
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/*
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* Define partitions for flash devices
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*/
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static struct mtd_partition partition_info[] = {
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{ .name = "Kernel",
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.offset = 0,
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.size = 3 * SZ_1M + SZ_512K },
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{ .name = "u-boot",
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.offset = 3 * SZ_1M + SZ_512K,
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.size = SZ_256K },
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{ .name = "u-boot params",
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.offset = 3 * SZ_1M + SZ_512K + SZ_256K,
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.size = SZ_256K },
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{ .name = "Amstrad LDR",
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.offset = 4 * SZ_1M,
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.size = SZ_256K },
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{ .name = "File system",
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.offset = 4 * SZ_1M + 1 * SZ_256K,
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.size = 27 * SZ_1M },
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{ .name = "PBL reserved",
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.offset = 32 * SZ_1M - 3 * SZ_256K,
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.size = 3 * SZ_256K },
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};
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/*
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* hardware specific access to control-lines
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*/
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static void ams_delta_hwcontrol(struct mtd_info *mtd, int cmd)
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{
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switch (cmd) {
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case NAND_CTL_SETCLE: T_NAND_CTL_SETCLE(cmd); break;
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case NAND_CTL_CLRCLE: T_NAND_CTL_CLRCLE(cmd); break;
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case NAND_CTL_SETALE: T_NAND_CTL_SETALE(cmd); break;
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case NAND_CTL_CLRALE: T_NAND_CTL_CLRALE(cmd); break;
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case NAND_CTL_SETNCE: T_NAND_CTL_SETNCE(cmd); break;
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case NAND_CTL_CLRNCE: T_NAND_CTL_CLRNCE(cmd); break;
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}
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}
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static void ams_delta_write_byte(struct mtd_info *mtd, u_char byte)
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{
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struct nand_chip *this = mtd->priv;
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omap_writew(0, (OMAP_MPUIO_BASE + OMAP_MPUIO_IO_CNTL));
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omap_writew(byte, this->IO_ADDR_W);
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ams_delta_latch2_write(AMS_DELTA_LATCH2_NAND_NWE, 0);
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ndelay(40);
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ams_delta_latch2_write(AMS_DELTA_LATCH2_NAND_NWE,
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AMS_DELTA_LATCH2_NAND_NWE);
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}
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static u_char ams_delta_read_byte(struct mtd_info *mtd)
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{
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u_char res;
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struct nand_chip *this = mtd->priv;
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ams_delta_latch2_write(AMS_DELTA_LATCH2_NAND_NRE, 0);
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ndelay(40);
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omap_writew(~0, (OMAP_MPUIO_BASE + OMAP_MPUIO_IO_CNTL));
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res = omap_readw(this->IO_ADDR_R);
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ams_delta_latch2_write(AMS_DELTA_LATCH2_NAND_NRE,
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AMS_DELTA_LATCH2_NAND_NRE);
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return res;
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}
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static void ams_delta_write_buf(struct mtd_info *mtd, const u_char *buf,
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int len)
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{
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int i;
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for (i=0; i<len; i++)
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ams_delta_write_byte(mtd, buf[i]);
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}
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static void ams_delta_read_buf(struct mtd_info *mtd, u_char *buf, int len)
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{
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int i;
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for (i=0; i<len; i++)
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buf[i] = ams_delta_read_byte(mtd);
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}
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static int ams_delta_verify_buf(struct mtd_info *mtd, const u_char *buf,
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int len)
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{
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int i;
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for (i=0; i<len; i++)
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if (buf[i] != ams_delta_read_byte(mtd))
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return -EFAULT;
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return 0;
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}
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static int ams_delta_nand_ready(struct mtd_info *mtd)
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{
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return omap_get_gpio_datain(AMS_DELTA_GPIO_PIN_NAND_RB);
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}
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/*
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* Main initialization routine
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*/
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static int __init ams_delta_init(void)
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{
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struct nand_chip *this;
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int err = 0;
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/* Allocate memory for MTD device structure and private data */
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ams_delta_mtd = kmalloc(sizeof(struct mtd_info) +
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sizeof(struct nand_chip), GFP_KERNEL);
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if (!ams_delta_mtd) {
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printk (KERN_WARNING "Unable to allocate E3 NAND MTD device structure.\n");
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err = -ENOMEM;
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goto out;
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}
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ams_delta_mtd->owner = THIS_MODULE;
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/* Get pointer to private data */
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this = (struct nand_chip *) (&ams_delta_mtd[1]);
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/* Initialize structures */
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memset(ams_delta_mtd, 0, sizeof(struct mtd_info));
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memset(this, 0, sizeof(struct nand_chip));
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/* Link the private data with the MTD structure */
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ams_delta_mtd->priv = this;
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/* Set address of NAND IO lines */
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this->IO_ADDR_R = (OMAP_MPUIO_BASE + OMAP_MPUIO_INPUT_LATCH);
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this->IO_ADDR_W = (OMAP_MPUIO_BASE + OMAP_MPUIO_OUTPUT);
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this->read_byte = ams_delta_read_byte;
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this->write_byte = ams_delta_write_byte;
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this->write_buf = ams_delta_write_buf;
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this->read_buf = ams_delta_read_buf;
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this->verify_buf = ams_delta_verify_buf;
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this->hwcontrol = ams_delta_hwcontrol;
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if (!omap_request_gpio(AMS_DELTA_GPIO_PIN_NAND_RB)) {
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this->dev_ready = ams_delta_nand_ready;
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} else {
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this->dev_ready = NULL;
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printk(KERN_NOTICE "Couldn't request gpio for Delta NAND ready.\n");
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}
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/* 25 us command delay time */
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this->chip_delay = 30;
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this->eccmode = NAND_ECC_SOFT;
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/* Set chip enabled, but */
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ams_delta_latch2_write(NAND_MASK, AMS_DELTA_LATCH2_NAND_NRE |
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AMS_DELTA_LATCH2_NAND_NWE |
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AMS_DELTA_LATCH2_NAND_NCE |
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AMS_DELTA_LATCH2_NAND_NWP);
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/* Scan to find existance of the device */
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if (nand_scan(ams_delta_mtd, 1)) {
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err = -ENXIO;
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goto out_mtd;
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}
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/* Register the partitions */
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add_mtd_partitions(ams_delta_mtd, partition_info,
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ARRAY_SIZE(partition_info));
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goto out;
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out_mtd:
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kfree(ams_delta_mtd);
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out:
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return err;
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}
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module_init(ams_delta_init);
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/*
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* Clean up routine
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*/
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static void __exit ams_delta_cleanup(void)
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{
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/* Release resources, unregister device */
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nand_release(ams_delta_mtd);
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/* Free the MTD device structure */
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kfree(ams_delta_mtd);
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}
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module_exit(ams_delta_cleanup);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Jonathan McDowell <noodles@earth.li>");
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MODULE_DESCRIPTION("Glue layer for NAND flash on Amstrad E3 (Delta)");
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