2007-05-09 01:00:38 +00:00
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/*
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* Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef MLX4_DEVICE_H
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#define MLX4_DEVICE_H
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#include <linux/pci.h>
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#include <linux/completion.h>
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#include <linux/radix-tree.h>
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2011-07-26 23:09:06 +00:00
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#include <linux/atomic.h>
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2007-05-09 01:00:38 +00:00
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2011-03-22 22:37:47 +00:00
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#define MAX_MSIX_P_PORT 17
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#define MAX_MSIX 64
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#define MSIX_LEGACY_SZ 4
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#define MIN_MSIX_P_PORT 5
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2007-05-09 01:00:38 +00:00
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enum {
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MLX4_FLAG_MSI_X = 1 << 0,
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2007-06-18 15:15:02 +00:00
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MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
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2011-12-13 04:10:33 +00:00
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MLX4_FLAG_MASTER = 1 << 2,
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MLX4_FLAG_SLAVE = 1 << 3,
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MLX4_FLAG_SRIOV = 1 << 4,
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2007-05-09 01:00:38 +00:00
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};
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enum {
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MLX4_MAX_PORTS = 2
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};
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2007-09-18 07:14:18 +00:00
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enum {
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MLX4_BOARD_ID_LEN = 64
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};
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2011-12-13 04:10:33 +00:00
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enum {
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MLX4_MAX_NUM_PF = 16,
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MLX4_MAX_NUM_VF = 64,
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MLX4_MFUNC_MAX = 80,
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net/mlx4_core: Fix number of EQs used in ICM initialisation
In SRIOV mode, the number of EQs used when computing the total ICM size
was incorrect.
To fix this, we do the following:
1. We add a new structure to mlx4_dev, mlx4_phys_caps, to contain physical HCA
capabilities. The PPF uses the phys capabilities when it computes things
like ICM size.
The dev_caps structure will then contain the paravirtualized values, making
bookkeeping much easier in SRIOV mode. We add a structure rather than a
single parameter because there will be other fields in the phys_caps.
The first field we add to the mlx4_phys_caps structure is num_phys_eqs.
2. In INIT_HCA, when running in SRIOV mode, the "log_num_eqs" parameter
passed to the FW is the number of EQs per VF/PF; each function (PF or VF)
has this number of EQs available.
However, the total number of EQs which must be allowed for in the ICM is
(1 << log_num_eqs) * (#VFs + #PFs). Rather than compute this quantity,
we allocate ICM space for 1024 EQs (which is the device maximum
number of EQs, and which is the value we place in the mlx4_phys_caps structure).
For INIT_HCA, however, we use the per-function number of EQs as described
above.
Signed-off-by: Marcel Apfelbaum <marcela@dev.mellanox.co.il>
Signed-off-by: Jack Morgenstein <jackm@dev.mellanox.co.il>
Reviewed-by: Or Gerlitz <ogerlitz@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2012-05-30 09:14:51 +00:00
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MLX4_MAX_EQ_NUM = 1024,
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2011-12-13 04:10:33 +00:00
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MLX4_MFUNC_EQ_NUM = 4,
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MLX4_MFUNC_MAX_EQES = 8,
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MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1)
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};
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2007-05-09 01:00:38 +00:00
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enum {
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2011-06-15 14:41:42 +00:00
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MLX4_DEV_CAP_FLAG_RC = 1LL << 0,
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MLX4_DEV_CAP_FLAG_UC = 1LL << 1,
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MLX4_DEV_CAP_FLAG_UD = 1LL << 2,
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2011-06-02 16:01:33 +00:00
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MLX4_DEV_CAP_FLAG_XRC = 1LL << 3,
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2011-06-15 14:41:42 +00:00
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MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6,
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MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7,
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MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
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MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
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MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12,
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MLX4_DEV_CAP_FLAG_BLH = 1LL << 15,
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MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16,
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MLX4_DEV_CAP_FLAG_APM = 1LL << 17,
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MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
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MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19,
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MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20,
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MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21,
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2011-07-07 19:19:29 +00:00
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MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30,
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MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32,
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2011-10-18 01:50:42 +00:00
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MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34,
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2011-11-26 19:55:15 +00:00
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MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37,
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MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38,
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2011-07-07 19:19:29 +00:00
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MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40,
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MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41,
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2011-06-15 14:47:14 +00:00
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MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42,
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2011-12-19 04:00:26 +00:00
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MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48,
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MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55
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2007-05-09 01:00:38 +00:00
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};
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2012-04-29 14:04:25 +00:00
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enum {
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MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0,
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MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1,
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MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2
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};
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2011-10-24 09:02:34 +00:00
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#define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
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2008-07-23 15:12:26 +00:00
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enum {
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MLX4_BMME_FLAG_LOCAL_INV = 1 << 6,
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MLX4_BMME_FLAG_REMOTE_INV = 1 << 7,
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MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
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MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
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MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
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};
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2007-05-09 01:00:38 +00:00
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enum mlx4_event {
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MLX4_EVENT_TYPE_COMP = 0x00,
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MLX4_EVENT_TYPE_PATH_MIG = 0x01,
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MLX4_EVENT_TYPE_COMM_EST = 0x02,
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MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
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MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
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MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
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MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
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MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
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MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
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MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
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MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
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MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
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MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
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MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
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MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
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MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
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MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
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2011-12-13 04:10:33 +00:00
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MLX4_EVENT_TYPE_CMD = 0x0a,
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MLX4_EVENT_TYPE_VEP_UPDATE = 0x19,
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MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18,
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2012-03-06 13:50:49 +00:00
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MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b,
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2011-12-13 04:10:33 +00:00
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MLX4_EVENT_TYPE_FLR_EVENT = 0x1c,
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MLX4_EVENT_TYPE_NONE = 0xff,
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2007-05-09 01:00:38 +00:00
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};
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enum {
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MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
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MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
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};
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2012-03-06 13:50:49 +00:00
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enum {
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MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0,
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};
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2007-05-09 01:00:38 +00:00
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enum {
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MLX4_PERM_LOCAL_READ = 1 << 10,
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MLX4_PERM_LOCAL_WRITE = 1 << 11,
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MLX4_PERM_REMOTE_READ = 1 << 12,
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MLX4_PERM_REMOTE_WRITE = 1 << 13,
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MLX4_PERM_ATOMIC = 1 << 14
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};
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enum {
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MLX4_OPCODE_NOP = 0x00,
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MLX4_OPCODE_SEND_INVAL = 0x01,
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MLX4_OPCODE_RDMA_WRITE = 0x08,
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MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
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MLX4_OPCODE_SEND = 0x0a,
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MLX4_OPCODE_SEND_IMM = 0x0b,
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MLX4_OPCODE_LSO = 0x0e,
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MLX4_OPCODE_RDMA_READ = 0x10,
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MLX4_OPCODE_ATOMIC_CS = 0x11,
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MLX4_OPCODE_ATOMIC_FA = 0x12,
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2010-04-14 14:23:39 +00:00
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MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14,
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MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15,
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2007-05-09 01:00:38 +00:00
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MLX4_OPCODE_BIND_MW = 0x18,
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MLX4_OPCODE_FMR = 0x19,
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MLX4_OPCODE_LOCAL_INVAL = 0x1b,
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MLX4_OPCODE_CONFIG_CMD = 0x1f,
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MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
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MLX4_RECV_OPCODE_SEND = 0x01,
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MLX4_RECV_OPCODE_SEND_IMM = 0x02,
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MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
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MLX4_CQE_OPCODE_ERROR = 0x1e,
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MLX4_CQE_OPCODE_RESIZE = 0x16,
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};
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enum {
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MLX4_STAT_RATE_OFFSET = 5
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};
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2010-12-02 11:44:49 +00:00
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enum mlx4_protocol {
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2011-03-22 22:38:17 +00:00
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MLX4_PROT_IB_IPV6 = 0,
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MLX4_PROT_ETH,
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MLX4_PROT_IB_IPV4,
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MLX4_PROT_FCOE
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2010-12-02 11:44:49 +00:00
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};
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2008-09-15 21:25:23 +00:00
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enum {
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MLX4_MTT_FLAG_PRESENT = 1
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};
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2008-10-22 17:25:29 +00:00
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enum mlx4_qp_region {
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MLX4_QP_REGION_FW = 0,
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MLX4_QP_REGION_ETH_ADDR,
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MLX4_QP_REGION_FC_ADDR,
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MLX4_QP_REGION_FC_EXCH,
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MLX4_NUM_QP_REGION
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};
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2008-10-22 22:38:42 +00:00
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enum mlx4_port_type {
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2011-12-13 04:10:33 +00:00
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MLX4_PORT_TYPE_NONE = 0,
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2009-03-19 02:45:11 +00:00
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MLX4_PORT_TYPE_IB = 1,
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MLX4_PORT_TYPE_ETH = 2,
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MLX4_PORT_TYPE_AUTO = 3
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2008-10-22 22:38:42 +00:00
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};
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2008-10-22 18:44:46 +00:00
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enum mlx4_special_vlan_idx {
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MLX4_NO_VLAN_IDX = 0,
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MLX4_VLAN_MISS_IDX,
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MLX4_VLAN_REGULAR
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};
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2011-03-22 22:38:17 +00:00
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enum mlx4_steer_type {
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MLX4_MC_STEER = 0,
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MLX4_UC_STEER,
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MLX4_NUM_STEERS
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};
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2008-10-22 17:25:29 +00:00
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enum {
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MLX4_NUM_FEXCH = 64 * 1024,
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};
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2010-10-07 14:24:16 +00:00
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enum {
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MLX4_MAX_FAST_REG_PAGES = 511,
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};
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IB/mlx4: Use multiple WQ blocks to post smaller send WQEs
ConnectX HCA supports shrinking WQEs, so that a single work request
can be made of multiple units of wqe_shift. This way, WRs can differ
in size, and do not have to be a power of 2 in size, saving memory and
speeding up send WR posting. Unfortunately, if we do this then the
wqe_index field in CQEs can't be used to look up the WR ID anymore, so
our implementation does this only if selective signaling is off.
Further, on 32-bit platforms, we can't use vmap() to make the QP
buffer virtually contigious. Thus we have to use constant-sized WRs to
make sure a WR is always fully within a single page-sized chunk.
Finally, we use WRs with the NOP opcode to avoid wrapping around the
queue buffer in the middle of posting a WR, and we set the
NoErrorCompletion bit to avoid getting completions with error for NOP
WRs. However, NEC is only supported starting with firmware 2.2.232,
so we use constant-sized WRs for older firmware. And, since MLX QPs
only support SEND, we use constant-sized WRs in this case.
When stamping during NOP posting, do stamping following setting of the
NOP WQE valid bit.
Signed-off-by: Michael S. Tsirkin <mst@dev.mellanox.co.il>
Signed-off-by: Jack Morgenstein <jackm@dev.mellanox.co.il>
Signed-off-by: Roland Dreier <rolandd@cisco.com>
2008-01-28 08:40:59 +00:00
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static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
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{
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return (major << 32) | (minor << 16) | subminor;
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}
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net/mlx4_core: Fix number of EQs used in ICM initialisation
In SRIOV mode, the number of EQs used when computing the total ICM size
was incorrect.
To fix this, we do the following:
1. We add a new structure to mlx4_dev, mlx4_phys_caps, to contain physical HCA
capabilities. The PPF uses the phys capabilities when it computes things
like ICM size.
The dev_caps structure will then contain the paravirtualized values, making
bookkeeping much easier in SRIOV mode. We add a structure rather than a
single parameter because there will be other fields in the phys_caps.
The first field we add to the mlx4_phys_caps structure is num_phys_eqs.
2. In INIT_HCA, when running in SRIOV mode, the "log_num_eqs" parameter
passed to the FW is the number of EQs per VF/PF; each function (PF or VF)
has this number of EQs available.
However, the total number of EQs which must be allowed for in the ICM is
(1 << log_num_eqs) * (#VFs + #PFs). Rather than compute this quantity,
we allocate ICM space for 1024 EQs (which is the device maximum
number of EQs, and which is the value we place in the mlx4_phys_caps structure).
For INIT_HCA, however, we use the per-function number of EQs as described
above.
Signed-off-by: Marcel Apfelbaum <marcela@dev.mellanox.co.il>
Signed-off-by: Jack Morgenstein <jackm@dev.mellanox.co.il>
Reviewed-by: Or Gerlitz <ogerlitz@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2012-05-30 09:14:51 +00:00
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|
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struct mlx4_phys_caps {
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u32 num_phys_eqs;
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};
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2007-05-09 01:00:38 +00:00
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|
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struct mlx4_caps {
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u64 fw_ver;
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2011-12-13 04:10:33 +00:00
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u32 function;
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2007-05-09 01:00:38 +00:00
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int num_ports;
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2007-06-18 15:15:02 +00:00
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|
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int vl_cap[MLX4_MAX_PORTS + 1];
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2008-10-22 17:56:48 +00:00
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|
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int ib_mtu_cap[MLX4_MAX_PORTS + 1];
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2008-11-29 05:29:46 +00:00
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|
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__be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
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2008-10-22 17:56:48 +00:00
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|
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u64 def_mac[MLX4_MAX_PORTS + 1];
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int eth_mtu_cap[MLX4_MAX_PORTS + 1];
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2007-06-18 15:15:02 +00:00
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int gid_table_len[MLX4_MAX_PORTS + 1];
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int pkey_table_len[MLX4_MAX_PORTS + 1];
|
2010-08-24 03:46:23 +00:00
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int trans_type[MLX4_MAX_PORTS + 1];
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int vendor_oui[MLX4_MAX_PORTS + 1];
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int wavelength[MLX4_MAX_PORTS + 1];
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u64 trans_code[MLX4_MAX_PORTS + 1];
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2007-05-09 01:00:38 +00:00
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int local_ca_ack_delay;
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int num_uars;
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2011-12-13 04:12:13 +00:00
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u32 uar_page_size;
|
2007-05-09 01:00:38 +00:00
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int bf_reg_size;
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int bf_regs_per_page;
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int max_sq_sg;
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int max_rq_sg;
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int num_qps;
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int max_wqes;
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int max_sq_desc_sz;
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int max_rq_desc_sz;
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int max_qp_init_rdma;
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int max_qp_dest_rdma;
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int sqp_start;
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int num_srqs;
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int max_srq_wqes;
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int max_srq_sge;
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int reserved_srqs;
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int num_cqs;
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int max_cqes;
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int reserved_cqs;
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int num_eqs;
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int reserved_eqs;
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2008-12-22 15:15:03 +00:00
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int num_comp_vectors;
|
2011-03-22 22:37:47 +00:00
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int comp_pool;
|
2007-05-09 01:00:38 +00:00
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int num_mpts;
|
2012-02-09 16:10:06 +00:00
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int max_fmr_maps;
|
2011-12-13 04:16:56 +00:00
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int num_mtts;
|
2007-05-09 01:00:38 +00:00
|
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int fmr_reserved_mtts;
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int reserved_mtts;
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int reserved_mrws;
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int reserved_uars;
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int num_mgms;
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int num_amgms;
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int reserved_mcgs;
|
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|
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int num_qp_per_mgm;
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|
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int num_pds;
|
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|
|
int reserved_pds;
|
2011-06-02 16:01:33 +00:00
|
|
|
int max_xrcds;
|
|
|
|
|
int reserved_xrcds;
|
2007-05-09 01:00:38 +00:00
|
|
|
int mtt_entry_sz;
|
2007-06-26 12:55:28 +00:00
|
|
|
u32 max_msg_sz;
|
2007-05-09 01:00:38 +00:00
|
|
|
u32 page_size_cap;
|
2011-06-15 14:41:42 +00:00
|
|
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u64 flags;
|
2012-04-29 14:04:25 +00:00
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|
|
u64 flags2;
|
2008-07-23 15:12:26 +00:00
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|
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u32 bmme_flags;
|
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|
|
u32 reserved_lkey;
|
2007-05-09 01:00:38 +00:00
|
|
|
u16 stat_rate_support;
|
2007-06-18 15:15:02 +00:00
|
|
|
u8 port_width_cap[MLX4_MAX_PORTS + 1];
|
2008-04-17 04:09:27 +00:00
|
|
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int max_gso_sz;
|
2012-04-29 14:04:25 +00:00
|
|
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int max_rss_tbl_sz;
|
2008-10-22 17:25:29 +00:00
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|
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int reserved_qps_cnt[MLX4_NUM_QP_REGION];
|
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int reserved_qps;
|
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int reserved_qps_base[MLX4_NUM_QP_REGION];
|
|
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|
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int log_num_macs;
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int log_num_vlans;
|
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|
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int log_num_prios;
|
2008-10-22 22:38:42 +00:00
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|
|
enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
|
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|
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u8 supported_type[MLX4_MAX_PORTS + 1];
|
2011-12-19 04:00:34 +00:00
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|
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u8 suggested_type[MLX4_MAX_PORTS + 1];
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|
|
u8 default_sense[MLX4_MAX_PORTS + 1];
|
2011-12-13 04:10:41 +00:00
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|
|
u32 port_mask[MLX4_MAX_PORTS + 1];
|
2009-03-19 02:45:11 +00:00
|
|
|
enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
|
2011-06-15 14:47:14 +00:00
|
|
|
u32 max_counters;
|
2012-01-11 17:02:17 +00:00
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|
|
u8 port_ib_mtu[MLX4_MAX_PORTS + 1];
|
2007-05-09 01:00:38 +00:00
|
|
|
};
|
|
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|
|
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|
|
struct mlx4_buf_list {
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|
void *buf;
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|
|
dma_addr_t map;
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|
|
};
|
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|
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|
|
struct mlx4_buf {
|
2008-02-07 05:17:59 +00:00
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|
|
struct mlx4_buf_list direct;
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|
|
struct mlx4_buf_list *page_list;
|
2007-05-09 01:00:38 +00:00
|
|
|
int nbufs;
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int npages;
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int page_shift;
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};
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struct mlx4_mtt {
|
2011-12-13 04:16:56 +00:00
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u32 offset;
|
2007-05-09 01:00:38 +00:00
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|
int order;
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|
int page_shift;
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|
|
};
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|
2008-04-23 18:55:45 +00:00
|
|
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enum {
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|
MLX4_DB_PER_PAGE = PAGE_SIZE / 4
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};
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struct mlx4_db_pgdir {
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struct list_head list;
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DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
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DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
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|
|
unsigned long *bits[2];
|
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|
|
__be32 *db_page;
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|
|
dma_addr_t db_dma;
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|
|
|
|
};
|
|
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|
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|
|
struct mlx4_ib_user_db_page;
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struct mlx4_db {
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|
__be32 *db;
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union {
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|
|
struct mlx4_db_pgdir *pgdir;
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|
struct mlx4_ib_user_db_page *user_page;
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|
} u;
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|
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|
|
dma_addr_t dma;
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|
|
int index;
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|
|
int order;
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|
};
|
|
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|
2008-04-25 21:27:08 +00:00
|
|
|
struct mlx4_hwq_resources {
|
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|
|
struct mlx4_db db;
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|
|
struct mlx4_mtt mtt;
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|
|
struct mlx4_buf buf;
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|
};
|
|
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|
2007-05-09 01:00:38 +00:00
|
|
|
struct mlx4_mr {
|
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|
|
struct mlx4_mtt mtt;
|
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|
|
u64 iova;
|
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|
|
u64 size;
|
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|
|
u32 key;
|
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|
|
u32 pd;
|
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|
|
u32 access;
|
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|
|
int enabled;
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|
};
|
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|
2007-08-01 09:29:05 +00:00
|
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struct mlx4_fmr {
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|
|
struct mlx4_mr mr;
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|
|
struct mlx4_mpt_entry *mpt;
|
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|
|
__be64 *mtts;
|
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|
|
dma_addr_t dma_handle;
|
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|
|
int max_pages;
|
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|
|
int max_maps;
|
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|
|
int maps;
|
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|
|
u8 page_shift;
|
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|
|
|
};
|
|
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|
|
2007-05-09 01:00:38 +00:00
|
|
|
struct mlx4_uar {
|
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|
|
|
unsigned long pfn;
|
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|
|
int index;
|
2011-03-22 22:38:41 +00:00
|
|
|
struct list_head bf_list;
|
|
|
|
|
unsigned free_bf_bmap;
|
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|
|
void __iomem *map;
|
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|
|
void __iomem *bf_map;
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|
|
|
};
|
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struct mlx4_bf {
|
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|
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unsigned long offset;
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|
|
int buf_size;
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|
|
struct mlx4_uar *uar;
|
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|
|
|
void __iomem *reg;
|
2007-05-09 01:00:38 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct mlx4_cq {
|
|
|
|
|
void (*comp) (struct mlx4_cq *);
|
|
|
|
|
void (*event) (struct mlx4_cq *, enum mlx4_event);
|
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|
|
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|
|
|
|
struct mlx4_uar *uar;
|
|
|
|
|
|
|
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|
|
u32 cons_index;
|
|
|
|
|
|
|
|
|
|
__be32 *set_ci_db;
|
|
|
|
|
__be32 *arm_db;
|
|
|
|
|
int arm_sn;
|
|
|
|
|
|
|
|
|
|
int cqn;
|
2008-12-22 15:15:03 +00:00
|
|
|
unsigned vector;
|
2007-05-09 01:00:38 +00:00
|
|
|
|
|
|
|
|
atomic_t refcount;
|
|
|
|
|
struct completion free;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct mlx4_qp {
|
|
|
|
|
void (*event) (struct mlx4_qp *, enum mlx4_event);
|
|
|
|
|
|
|
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|
|
int qpn;
|
|
|
|
|
|
|
|
|
|
atomic_t refcount;
|
|
|
|
|
struct completion free;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct mlx4_srq {
|
|
|
|
|
void (*event) (struct mlx4_srq *, enum mlx4_event);
|
|
|
|
|
|
|
|
|
|
int srqn;
|
|
|
|
|
int max;
|
|
|
|
|
int max_gs;
|
|
|
|
|
int wqe_shift;
|
|
|
|
|
|
|
|
|
|
atomic_t refcount;
|
|
|
|
|
struct completion free;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct mlx4_av {
|
|
|
|
|
__be32 port_pd;
|
|
|
|
|
u8 reserved1;
|
|
|
|
|
u8 g_slid;
|
|
|
|
|
__be16 dlid;
|
|
|
|
|
u8 reserved2;
|
|
|
|
|
u8 gid_index;
|
|
|
|
|
u8 stat_rate;
|
|
|
|
|
u8 hop_limit;
|
|
|
|
|
__be32 sl_tclass_flowlabel;
|
|
|
|
|
u8 dgid[16];
|
|
|
|
|
};
|
|
|
|
|
|
2010-10-25 04:08:52 +00:00
|
|
|
struct mlx4_eth_av {
|
|
|
|
|
__be32 port_pd;
|
|
|
|
|
u8 reserved1;
|
|
|
|
|
u8 smac_idx;
|
|
|
|
|
u16 reserved2;
|
|
|
|
|
u8 reserved3;
|
|
|
|
|
u8 gid_index;
|
|
|
|
|
u8 stat_rate;
|
|
|
|
|
u8 hop_limit;
|
|
|
|
|
__be32 sl_tclass_flowlabel;
|
|
|
|
|
u8 dgid[16];
|
|
|
|
|
u32 reserved4[2];
|
|
|
|
|
__be16 vlan;
|
|
|
|
|
u8 mac[6];
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
union mlx4_ext_av {
|
|
|
|
|
struct mlx4_av ib;
|
|
|
|
|
struct mlx4_eth_av eth;
|
|
|
|
|
};
|
|
|
|
|
|
2011-06-15 14:47:14 +00:00
|
|
|
struct mlx4_counter {
|
|
|
|
|
u8 reserved1[3];
|
|
|
|
|
u8 counter_mode;
|
|
|
|
|
__be32 num_ifc;
|
|
|
|
|
u32 reserved2[2];
|
|
|
|
|
__be64 rx_frames;
|
|
|
|
|
__be64 rx_bytes;
|
|
|
|
|
__be64 tx_frames;
|
|
|
|
|
__be64 tx_bytes;
|
|
|
|
|
};
|
|
|
|
|
|
2007-05-09 01:00:38 +00:00
|
|
|
struct mlx4_dev {
|
|
|
|
|
struct pci_dev *pdev;
|
|
|
|
|
unsigned long flags;
|
2011-12-13 04:10:33 +00:00
|
|
|
unsigned long num_slaves;
|
2007-05-09 01:00:38 +00:00
|
|
|
struct mlx4_caps caps;
|
net/mlx4_core: Fix number of EQs used in ICM initialisation
In SRIOV mode, the number of EQs used when computing the total ICM size
was incorrect.
To fix this, we do the following:
1. We add a new structure to mlx4_dev, mlx4_phys_caps, to contain physical HCA
capabilities. The PPF uses the phys capabilities when it computes things
like ICM size.
The dev_caps structure will then contain the paravirtualized values, making
bookkeeping much easier in SRIOV mode. We add a structure rather than a
single parameter because there will be other fields in the phys_caps.
The first field we add to the mlx4_phys_caps structure is num_phys_eqs.
2. In INIT_HCA, when running in SRIOV mode, the "log_num_eqs" parameter
passed to the FW is the number of EQs per VF/PF; each function (PF or VF)
has this number of EQs available.
However, the total number of EQs which must be allowed for in the ICM is
(1 << log_num_eqs) * (#VFs + #PFs). Rather than compute this quantity,
we allocate ICM space for 1024 EQs (which is the device maximum
number of EQs, and which is the value we place in the mlx4_phys_caps structure).
For INIT_HCA, however, we use the per-function number of EQs as described
above.
Signed-off-by: Marcel Apfelbaum <marcela@dev.mellanox.co.il>
Signed-off-by: Jack Morgenstein <jackm@dev.mellanox.co.il>
Reviewed-by: Or Gerlitz <ogerlitz@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2012-05-30 09:14:51 +00:00
|
|
|
struct mlx4_phys_caps phys_caps;
|
2007-05-09 01:00:38 +00:00
|
|
|
struct radix_tree_root qp_table_tree;
|
2011-03-22 22:38:07 +00:00
|
|
|
u8 rev_id;
|
2007-09-18 07:14:18 +00:00
|
|
|
char board_id[MLX4_BOARD_ID_LEN];
|
mlx4_core: Modify driver initialization flow to accommodate SRIOV for Ethernet
1. Added module parameters sr_iov and probe_vf for controlling enablement of
SRIOV mode.
2. Increased default max num-qps, num-mpts and log_num_macs to accomodate
SRIOV mode
3. Added port_type_array as a module parameter to allow driver startup with
ports configured as desired.
In SRIOV mode, only ETH is supported, and this array is ignored; otherwise,
for the case where the FW supports both port types (ETH and IB), the
port_type_array parameter is used.
By default, the port_type_array is set to configure both ports as IB.
4. When running in sriov mode, the master needs to initialize the ICM eq table
to hold the eq's for itself and also for all the slaves.
5. mlx4_set_port_mask() now invoked from mlx4_init_hca, instead of in mlx4_dev_cap.
6. Introduced sriov VF (slave) device startup/teardown logic (mainly procedures
mlx4_init_slave, mlx4_slave_exit, mlx4_slave_cap, mlx4_slave_exit and flow
modifications in __mlx4_init_one, mlx4_init_hca, and mlx4_setup_hca).
VFs obtain their startup information from the PF (master) device via the
comm channel.
7. In SRIOV mode (both PF and VF), MSI_X must be enabled, or the driver
aborts loading the device.
8. Do not allow setting port type via sysfs when running in SRIOV mode.
9. mlx4_get_ownership: Currently, only one PF is supported by the driver.
If the HCA is burned with FW which enables more than one PF, only one
of the PFs is allowed to run. The first one up grabs a FW ownership
semaphone -- all other PFs will find that semaphore taken, and the
driver will not allow them to run.
Signed-off-by: Jack Morgenstein <jackm@dev.mellanox.co.il>
Signed-off-by: Yevgeny Petrilin <yevgenyp@mellanox.co.il>
Signed-off-by: Liran Liss <liranl@mellanox.co.il>
Signed-off-by: Marcel Apfelbaum <marcela@mellanox.co.il>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-12-13 04:18:30 +00:00
|
|
|
int num_vfs;
|
2007-05-09 01:00:38 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct mlx4_init_port_param {
|
|
|
|
|
int set_guid0;
|
|
|
|
|
int set_node_guid;
|
|
|
|
|
int set_si_guid;
|
|
|
|
|
u16 mtu;
|
|
|
|
|
int port_width_cap;
|
|
|
|
|
u16 vl_cap;
|
|
|
|
|
u16 max_gid;
|
|
|
|
|
u16 max_pkey;
|
|
|
|
|
u64 guid0;
|
|
|
|
|
u64 node_guid;
|
|
|
|
|
u64 si_guid;
|
|
|
|
|
};
|
|
|
|
|
|
2008-10-22 22:38:42 +00:00
|
|
|
#define mlx4_foreach_port(port, dev, type) \
|
|
|
|
|
for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
|
2011-12-13 04:10:41 +00:00
|
|
|
if ((type) == (dev)->caps.port_mask[(port)])
|
2008-10-22 22:38:42 +00:00
|
|
|
|
2011-12-13 04:10:41 +00:00
|
|
|
#define mlx4_foreach_ib_transport_port(port, dev) \
|
|
|
|
|
for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
|
|
|
|
|
if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
|
|
|
|
|
((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
|
2011-12-13 04:10:33 +00:00
|
|
|
|
|
|
|
|
static inline int mlx4_is_master(struct mlx4_dev *dev)
|
|
|
|
|
{
|
|
|
|
|
return dev->flags & MLX4_FLAG_MASTER;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn)
|
|
|
|
|
{
|
|
|
|
|
return (qpn < dev->caps.sqp_start + 8);
|
|
|
|
|
}
|
2010-10-25 04:08:52 +00:00
|
|
|
|
2011-12-13 04:10:33 +00:00
|
|
|
static inline int mlx4_is_mfunc(struct mlx4_dev *dev)
|
|
|
|
|
{
|
|
|
|
|
return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline int mlx4_is_slave(struct mlx4_dev *dev)
|
|
|
|
|
{
|
|
|
|
|
return dev->flags & MLX4_FLAG_SLAVE;
|
|
|
|
|
}
|
2010-10-25 04:08:52 +00:00
|
|
|
|
2007-05-09 01:00:38 +00:00
|
|
|
int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
|
|
|
|
|
struct mlx4_buf *buf);
|
|
|
|
|
void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
|
2008-02-07 05:07:54 +00:00
|
|
|
static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
|
|
|
|
|
{
|
2008-01-28 08:40:51 +00:00
|
|
|
if (BITS_PER_LONG == 64 || buf->nbufs == 1)
|
2008-02-07 05:17:59 +00:00
|
|
|
return buf->direct.buf + offset;
|
2008-02-07 05:07:54 +00:00
|
|
|
else
|
2008-02-07 05:17:59 +00:00
|
|
|
return buf->page_list[offset >> PAGE_SHIFT].buf +
|
2008-02-07 05:07:54 +00:00
|
|
|
(offset & (PAGE_SIZE - 1));
|
|
|
|
|
}
|
2007-05-09 01:00:38 +00:00
|
|
|
|
|
|
|
|
int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
|
|
|
|
|
void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
|
2011-06-02 16:01:33 +00:00
|
|
|
int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
|
|
|
|
|
void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
|
2007-05-09 01:00:38 +00:00
|
|
|
|
|
|
|
|
int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
|
|
|
|
|
void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
|
2011-03-22 22:38:41 +00:00
|
|
|
int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf);
|
|
|
|
|
void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf);
|
2007-05-09 01:00:38 +00:00
|
|
|
|
|
|
|
|
int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
|
|
|
|
|
struct mlx4_mtt *mtt);
|
|
|
|
|
void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
|
|
|
|
|
u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
|
|
|
|
|
|
|
|
|
|
int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
|
|
|
|
|
int npages, int page_shift, struct mlx4_mr *mr);
|
|
|
|
|
void mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
|
|
|
|
|
int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
|
|
|
|
|
int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
|
|
|
|
|
int start_index, int npages, u64 *page_list);
|
|
|
|
|
int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
|
|
|
|
|
struct mlx4_buf *buf);
|
|
|
|
|
|
2008-04-23 18:55:45 +00:00
|
|
|
int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order);
|
|
|
|
|
void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
|
|
|
|
|
|
2008-04-25 21:27:08 +00:00
|
|
|
int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
|
|
|
|
|
int size, int max_direct);
|
|
|
|
|
void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
|
|
|
|
|
int size);
|
|
|
|
|
|
2007-05-09 01:00:38 +00:00
|
|
|
int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
|
2008-04-29 20:46:50 +00:00
|
|
|
struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
|
2008-12-22 15:15:03 +00:00
|
|
|
unsigned vector, int collapsed);
|
2007-05-09 01:00:38 +00:00
|
|
|
void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
|
|
|
|
|
|
2008-10-10 19:01:37 +00:00
|
|
|
int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base);
|
|
|
|
|
void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
|
|
|
|
|
|
|
|
|
|
int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp);
|
2007-05-09 01:00:38 +00:00
|
|
|
void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
|
|
|
|
|
|
2011-06-02 17:43:26 +00:00
|
|
|
int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn,
|
|
|
|
|
struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq);
|
2007-05-09 01:00:38 +00:00
|
|
|
void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
|
|
|
|
|
int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
|
2007-06-21 10:03:11 +00:00
|
|
|
int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
|
2007-05-09 01:00:38 +00:00
|
|
|
|
2007-06-18 15:15:02 +00:00
|
|
|
int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
|
2007-05-09 01:00:38 +00:00
|
|
|
int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
|
|
|
|
|
|
2011-12-13 04:16:21 +00:00
|
|
|
int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
|
|
|
|
|
int block_mcast_loopback, enum mlx4_protocol prot);
|
|
|
|
|
int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
|
|
|
|
|
enum mlx4_protocol prot);
|
2008-07-15 06:48:48 +00:00
|
|
|
int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
|
2010-12-02 11:44:49 +00:00
|
|
|
int block_mcast_loopback, enum mlx4_protocol protocol);
|
|
|
|
|
int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
|
|
|
|
|
enum mlx4_protocol protocol);
|
2011-03-22 22:38:31 +00:00
|
|
|
int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
|
|
|
|
|
int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
|
|
|
|
|
int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
|
|
|
|
|
int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
|
|
|
|
|
int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
|
|
|
|
|
|
2011-12-13 04:16:21 +00:00
|
|
|
int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
|
|
|
|
|
void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
|
|
|
|
|
int mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
|
|
|
|
|
int mlx4_get_eth_qp(struct mlx4_dev *dev, u8 port, u64 mac, int *qpn);
|
|
|
|
|
void mlx4_put_eth_qp(struct mlx4_dev *dev, u8 port, u64 mac, int qpn);
|
2012-01-19 09:45:05 +00:00
|
|
|
void mlx4_set_stats_bitmap(struct mlx4_dev *dev, u64 *stats_bitmap);
|
2012-03-06 04:04:47 +00:00
|
|
|
int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
|
|
|
|
|
u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
|
|
|
|
|
int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
|
|
|
|
|
u8 promisc);
|
2012-04-04 21:33:25 +00:00
|
|
|
int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc);
|
|
|
|
|
int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw,
|
|
|
|
|
u8 *pg, u16 *ratelimit);
|
2010-08-26 14:19:22 +00:00
|
|
|
int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
|
2008-10-22 18:44:46 +00:00
|
|
|
int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
|
|
|
|
|
void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index);
|
|
|
|
|
|
2007-08-01 09:29:05 +00:00
|
|
|
int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
|
|
|
|
|
int npages, u64 iova, u32 *lkey, u32 *rkey);
|
|
|
|
|
int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
|
|
|
|
|
int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
|
|
|
|
|
int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
|
|
|
|
|
void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
|
|
|
|
|
u32 *lkey, u32 *rkey);
|
|
|
|
|
int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
|
|
|
|
|
int mlx4_SYNC_TPT(struct mlx4_dev *dev);
|
2010-08-24 03:46:18 +00:00
|
|
|
int mlx4_test_interrupts(struct mlx4_dev *dev);
|
2011-03-22 22:37:47 +00:00
|
|
|
int mlx4_assign_eq(struct mlx4_dev *dev, char* name , int* vector);
|
|
|
|
|
void mlx4_release_eq(struct mlx4_dev *dev, int vec);
|
2007-08-01 09:29:05 +00:00
|
|
|
|
2011-03-22 22:37:59 +00:00
|
|
|
int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port);
|
|
|
|
|
int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);
|
|
|
|
|
|
2011-06-15 14:47:14 +00:00
|
|
|
int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
|
|
|
|
|
void mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
|
|
|
|
|
|
2007-05-09 01:00:38 +00:00
|
|
|
#endif /* MLX4_DEVICE_H */
|