2005-04-16 22:20:36 +00:00
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#ifndef __SOUND_CS4231_H
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#define __SOUND_CS4231_H
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/*
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* Copyright (c) by Jaroslav Kysela <perex@suse.cz>
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* Definitions for CS4231 & InterWave chips & compatible chips
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include "control.h"
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#include "pcm.h"
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#include "timer.h"
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/* IO ports */
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#define CS4231P(x) (c_d_c_CS4231##x)
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#define c_d_c_CS4231REGSEL 0
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#define c_d_c_CS4231REG 1
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#define c_d_c_CS4231STATUS 2
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#define c_d_c_CS4231PIO 3
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/* codec registers */
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#define CS4231_LEFT_INPUT 0x00 /* left input control */
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#define CS4231_RIGHT_INPUT 0x01 /* right input control */
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#define CS4231_AUX1_LEFT_INPUT 0x02 /* left AUX1 input control */
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#define CS4231_AUX1_RIGHT_INPUT 0x03 /* right AUX1 input control */
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#define CS4231_AUX2_LEFT_INPUT 0x04 /* left AUX2 input control */
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#define CS4231_AUX2_RIGHT_INPUT 0x05 /* right AUX2 input control */
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#define CS4231_LEFT_OUTPUT 0x06 /* left output control register */
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#define CS4231_RIGHT_OUTPUT 0x07 /* right output control register */
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#define CS4231_PLAYBK_FORMAT 0x08 /* clock and data format - playback - bits 7-0 MCE */
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#define CS4231_IFACE_CTRL 0x09 /* interface control - bits 7-2 MCE */
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#define CS4231_PIN_CTRL 0x0a /* pin control */
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#define CS4231_TEST_INIT 0x0b /* test and initialization */
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#define CS4231_MISC_INFO 0x0c /* miscellaneaous information */
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#define CS4231_LOOPBACK 0x0d /* loopback control */
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#define CS4231_PLY_UPR_CNT 0x0e /* playback upper base count */
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#define CS4231_PLY_LWR_CNT 0x0f /* playback lower base count */
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#define CS4231_ALT_FEATURE_1 0x10 /* alternate #1 feature enable */
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#define AD1845_AF1_MIC_LEFT 0x10 /* alternate #1 feature + MIC left */
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#define CS4231_ALT_FEATURE_2 0x11 /* alternate #2 feature enable */
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#define AD1845_AF2_MIC_RIGHT 0x11 /* alternate #2 feature + MIC right */
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#define CS4231_LEFT_LINE_IN 0x12 /* left line input control */
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#define CS4231_RIGHT_LINE_IN 0x13 /* right line input control */
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#define CS4231_TIMER_LOW 0x14 /* timer low byte */
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#define CS4231_TIMER_HIGH 0x15 /* timer high byte */
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#define CS4231_LEFT_MIC_INPUT 0x16 /* left MIC input control register (InterWave only) */
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#define AD1845_UPR_FREQ_SEL 0x16 /* upper byte of frequency select */
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#define CS4231_RIGHT_MIC_INPUT 0x17 /* right MIC input control register (InterWave only) */
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#define AD1845_LWR_FREQ_SEL 0x17 /* lower byte of frequency select */
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#define CS4236_EXT_REG 0x17 /* extended register access */
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#define CS4231_IRQ_STATUS 0x18 /* irq status register */
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#define CS4231_LINE_LEFT_OUTPUT 0x19 /* left line output control register (InterWave only) */
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#define CS4231_VERSION 0x19 /* CS4231(A) - version values */
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#define CS4231_MONO_CTRL 0x1a /* mono input/output control */
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#define CS4231_LINE_RIGHT_OUTPUT 0x1b /* right line output control register (InterWave only) */
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#define AD1845_PWR_DOWN 0x1b /* power down control */
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#define CS4235_LEFT_MASTER 0x1b /* left master output control */
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#define CS4231_REC_FORMAT 0x1c /* clock and data format - record - bits 7-0 MCE */
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#define CS4231_PLY_VAR_FREQ 0x1d /* playback variable frequency */
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#define AD1845_CLOCK 0x1d /* crystal clock select and total power down */
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#define CS4235_RIGHT_MASTER 0x1d /* right master output control */
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#define CS4231_REC_UPR_CNT 0x1e /* record upper count */
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#define CS4231_REC_LWR_CNT 0x1f /* record lower count */
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/* definitions for codec register select port - CODECP( REGSEL ) */
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#define CS4231_INIT 0x80 /* CODEC is initializing */
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#define CS4231_MCE 0x40 /* mode change enable */
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#define CS4231_TRD 0x20 /* transfer request disable */
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/* definitions for codec status register - CODECP( STATUS ) */
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#define CS4231_GLOBALIRQ 0x01 /* IRQ is active */
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/* definitions for codec irq status */
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#define CS4231_PLAYBACK_IRQ 0x10
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#define CS4231_RECORD_IRQ 0x20
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#define CS4231_TIMER_IRQ 0x40
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#define CS4231_ALL_IRQS 0x70
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#define CS4231_REC_UNDERRUN 0x08
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#define CS4231_REC_OVERRUN 0x04
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#define CS4231_PLY_OVERRUN 0x02
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#define CS4231_PLY_UNDERRUN 0x01
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/* definitions for CS4231_LEFT_INPUT and CS4231_RIGHT_INPUT registers */
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#define CS4231_ENABLE_MIC_GAIN 0x20
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#define CS4231_MIXS_LINE 0x00
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#define CS4231_MIXS_AUX1 0x40
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#define CS4231_MIXS_MIC 0x80
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#define CS4231_MIXS_ALL 0xc0
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/* definitions for clock and data format register - CS4231_PLAYBK_FORMAT */
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#define CS4231_LINEAR_8 0x00 /* 8-bit unsigned data */
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#define CS4231_ALAW_8 0x60 /* 8-bit A-law companded */
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#define CS4231_ULAW_8 0x20 /* 8-bit U-law companded */
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#define CS4231_LINEAR_16 0x40 /* 16-bit twos complement data - little endian */
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#define CS4231_LINEAR_16_BIG 0xc0 /* 16-bit twos complement data - big endian */
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#define CS4231_ADPCM_16 0xa0 /* 16-bit ADPCM */
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#define CS4231_STEREO 0x10 /* stereo mode */
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/* bits 3-1 define frequency divisor */
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#define CS4231_XTAL1 0x00 /* 24.576 crystal */
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#define CS4231_XTAL2 0x01 /* 16.9344 crystal */
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/* definitions for interface control register - CS4231_IFACE_CTRL */
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#define CS4231_RECORD_PIO 0x80 /* record PIO enable */
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#define CS4231_PLAYBACK_PIO 0x40 /* playback PIO enable */
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#define CS4231_CALIB_MODE 0x18 /* calibration mode bits */
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#define CS4231_AUTOCALIB 0x08 /* auto calibrate */
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#define CS4231_SINGLE_DMA 0x04 /* use single DMA channel */
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#define CS4231_RECORD_ENABLE 0x02 /* record enable */
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#define CS4231_PLAYBACK_ENABLE 0x01 /* playback enable */
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/* definitions for pin control register - CS4231_PIN_CTRL */
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#define CS4231_IRQ_ENABLE 0x02 /* enable IRQ */
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#define CS4231_XCTL1 0x40 /* external control #1 */
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#define CS4231_XCTL0 0x80 /* external control #0 */
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/* definitions for test and init register - CS4231_TEST_INIT */
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#define CS4231_CALIB_IN_PROGRESS 0x20 /* auto calibrate in progress */
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#define CS4231_DMA_REQUEST 0x10 /* DMA request in progress */
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/* definitions for misc control register - CS4231_MISC_INFO */
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#define CS4231_MODE2 0x40 /* MODE 2 */
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#define CS4231_IW_MODE3 0x6c /* MODE 3 - InterWave enhanced mode */
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#define CS4231_4236_MODE3 0xe0 /* MODE 3 - CS4236+ enhanced mode */
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/* definitions for alternate feature 1 register - CS4231_ALT_FEATURE_1 */
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#define CS4231_DACZ 0x01 /* zero DAC when underrun */
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#define CS4231_TIMER_ENABLE 0x40 /* codec timer enable */
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#define CS4231_OLB 0x80 /* output level bit */
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/* definitions for Extended Registers - CS4236+ */
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#define CS4236_REG(i23val) (((i23val << 2) & 0x10) | ((i23val >> 4) & 0x0f))
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#define CS4236_I23VAL(reg) ((((reg)&0xf) << 4) | (((reg)&0x10) >> 2) | 0x8)
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#define CS4236_LEFT_LINE 0x08 /* left LINE alternate volume */
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#define CS4236_RIGHT_LINE 0x18 /* right LINE alternate volume */
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#define CS4236_LEFT_MIC 0x28 /* left MIC volume */
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#define CS4236_RIGHT_MIC 0x38 /* right MIC volume */
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#define CS4236_LEFT_MIX_CTRL 0x48 /* synthesis and left input mixer control */
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#define CS4236_RIGHT_MIX_CTRL 0x58 /* right input mixer control */
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#define CS4236_LEFT_FM 0x68 /* left FM volume */
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#define CS4236_RIGHT_FM 0x78 /* right FM volume */
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#define CS4236_LEFT_DSP 0x88 /* left DSP serial port volume */
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#define CS4236_RIGHT_DSP 0x98 /* right DSP serial port volume */
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#define CS4236_RIGHT_LOOPBACK 0xa8 /* right loopback monitor volume */
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#define CS4236_DAC_MUTE 0xb8 /* DAC mute and IFSE enable */
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#define CS4236_ADC_RATE 0xc8 /* indenpendent ADC sample frequency */
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#define CS4236_DAC_RATE 0xd8 /* indenpendent DAC sample frequency */
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#define CS4236_LEFT_MASTER 0xe8 /* left master digital audio volume */
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#define CS4236_RIGHT_MASTER 0xf8 /* right master digital audio volume */
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#define CS4236_LEFT_WAVE 0x0c /* left wavetable serial port volume */
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#define CS4236_RIGHT_WAVE 0x1c /* right wavetable serial port volume */
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#define CS4236_VERSION 0x9c /* chip version and ID */
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/* defines for codec.mode */
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#define CS4231_MODE_NONE 0x0000
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#define CS4231_MODE_PLAY 0x0001
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#define CS4231_MODE_RECORD 0x0002
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#define CS4231_MODE_TIMER 0x0004
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#define CS4231_MODE_OPEN (CS4231_MODE_PLAY|CS4231_MODE_RECORD|CS4231_MODE_TIMER)
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/* defines for codec.hardware */
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#define CS4231_HW_DETECT 0x0000 /* let CS4231 driver detect chip */
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#define CS4231_HW_DETECT3 0x0001 /* allow mode 3 */
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#define CS4231_HW_TYPE_MASK 0xff00 /* type mask */
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#define CS4231_HW_CS4231_MASK 0x0100 /* CS4231 serie */
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#define CS4231_HW_CS4231 0x0100 /* CS4231 chip */
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#define CS4231_HW_CS4231A 0x0101 /* CS4231A chip */
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#define CS4231_HW_AD1845 0x0102 /* AD1845 chip */
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#define CS4231_HW_CS4232_MASK 0x0200 /* CS4232 serie (has control ports) */
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#define CS4231_HW_CS4232 0x0200 /* CS4232 */
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#define CS4231_HW_CS4232A 0x0201 /* CS4232A */
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#define CS4231_HW_CS4236 0x0202 /* CS4236 */
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#define CS4231_HW_CS4236B_MASK 0x0400 /* CS4236B serie (has extended control regs) */
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#define CS4231_HW_CS4235 0x0400 /* CS4235 - Crystal Clear (tm) stereo enhancement */
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#define CS4231_HW_CS4236B 0x0401 /* CS4236B */
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#define CS4231_HW_CS4237B 0x0402 /* CS4237B - SRS 3D */
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#define CS4231_HW_CS4238B 0x0403 /* CS4238B - QSOUND 3D */
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#define CS4231_HW_CS4239 0x0404 /* CS4239 - Crystal Clear (tm) stereo enhancement */
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/* compatible, but clones */
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#define CS4231_HW_INTERWAVE 0x1000 /* InterWave chip */
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#define CS4231_HW_OPL3SA2 0x1001 /* OPL3-SA2 chip */
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/* defines for codec.hwshare */
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#define CS4231_HWSHARE_IRQ (1<<0)
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#define CS4231_HWSHARE_DMA1 (1<<1)
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#define CS4231_HWSHARE_DMA2 (1<<2)
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2005-11-17 13:30:42 +00:00
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struct snd_cs4231 {
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unsigned long port; /* base i/o port */
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struct resource *res_port;
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unsigned long cport; /* control base i/o port (CS4236) */
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struct resource *res_cport;
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int irq; /* IRQ line */
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int dma1; /* playback DMA */
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int dma2; /* record DMA */
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unsigned short version; /* version of CODEC chip */
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unsigned short mode; /* see to CS4231_MODE_XXXX */
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unsigned short hardware; /* see to CS4231_HW_XXXX */
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unsigned short hwshare; /* shared resources */
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unsigned short single_dma:1, /* forced single DMA mode (GUS 16-bit daughter board) or dma1 == dma2 */
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ebus_flag:1; /* SPARC: EBUS present */
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2005-11-17 13:30:42 +00:00
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struct snd_card *card;
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struct snd_pcm *pcm;
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struct snd_pcm_substream *playback_substream;
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struct snd_pcm_substream *capture_substream;
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struct snd_timer *timer;
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2005-04-16 22:20:36 +00:00
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unsigned char image[32]; /* registers image */
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unsigned char eimage[32]; /* extended registers image */
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unsigned char cimage[16]; /* control registers image */
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int mce_bit;
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int calibrate_mute;
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int sw_3d_bit;
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unsigned int p_dma_size;
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unsigned int c_dma_size;
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spinlock_t reg_lock;
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2006-01-16 15:33:08 +00:00
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struct mutex mce_mutex;
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struct mutex open_mutex;
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2005-04-16 22:20:36 +00:00
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int (*rate_constraint) (struct snd_pcm_runtime *runtime);
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void (*set_playback_format) (struct snd_cs4231 *chip, struct snd_pcm_hw_params *hw_params, unsigned char pdfr);
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void (*set_capture_format) (struct snd_cs4231 *chip, struct snd_pcm_hw_params *hw_params, unsigned char cdfr);
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void (*trigger) (struct snd_cs4231 *chip, unsigned int what, int start);
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#ifdef CONFIG_PM
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void (*suspend) (struct snd_cs4231 *chip);
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void (*resume) (struct snd_cs4231 *chip);
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2005-04-16 22:20:36 +00:00
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#endif
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void *dma_private_data;
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2005-11-17 13:30:42 +00:00
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int (*claim_dma) (struct snd_cs4231 *chip, void *dma_private_data, int dma);
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int (*release_dma) (struct snd_cs4231 *chip, void *dma_private_data, int dma);
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2005-04-16 22:20:36 +00:00
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};
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/* exported functions */
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2005-11-17 13:30:42 +00:00
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void snd_cs4231_out(struct snd_cs4231 *chip, unsigned char reg, unsigned char val);
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unsigned char snd_cs4231_in(struct snd_cs4231 *chip, unsigned char reg);
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void snd_cs4236_ext_out(struct snd_cs4231 *chip, unsigned char reg, unsigned char val);
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unsigned char snd_cs4236_ext_in(struct snd_cs4231 *chip, unsigned char reg);
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void snd_cs4231_mce_up(struct snd_cs4231 *chip);
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void snd_cs4231_mce_down(struct snd_cs4231 *chip);
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2005-04-16 22:20:36 +00:00
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IRQ: Maintain regs pointer globally rather than passing to IRQ handlers
Maintain a per-CPU global "struct pt_regs *" variable which can be used instead
of passing regs around manually through all ~1800 interrupt handlers in the
Linux kernel.
The regs pointer is used in few places, but it potentially costs both stack
space and code to pass it around. On the FRV arch, removing the regs parameter
from all the genirq function results in a 20% speed up of the IRQ exit path
(ie: from leaving timer_interrupt() to leaving do_IRQ()).
Where appropriate, an arch may override the generic storage facility and do
something different with the variable. On FRV, for instance, the address is
maintained in GR28 at all times inside the kernel as part of general exception
handling.
Having looked over the code, it appears that the parameter may be handed down
through up to twenty or so layers of functions. Consider a USB character
device attached to a USB hub, attached to a USB controller that posts its
interrupts through a cascaded auxiliary interrupt controller. A character
device driver may want to pass regs to the sysrq handler through the input
layer which adds another few layers of parameter passing.
I've build this code with allyesconfig for x86_64 and i386. I've runtested the
main part of the code on FRV and i386, though I can't test most of the drivers.
I've also done partial conversion for powerpc and MIPS - these at least compile
with minimal configurations.
This will affect all archs. Mostly the changes should be relatively easy.
Take do_IRQ(), store the regs pointer at the beginning, saving the old one:
struct pt_regs *old_regs = set_irq_regs(regs);
And put the old one back at the end:
set_irq_regs(old_regs);
Don't pass regs through to generic_handle_irq() or __do_IRQ().
In timer_interrupt(), this sort of change will be necessary:
- update_process_times(user_mode(regs));
- profile_tick(CPU_PROFILING, regs);
+ update_process_times(user_mode(get_irq_regs()));
+ profile_tick(CPU_PROFILING);
I'd like to move update_process_times()'s use of get_irq_regs() into itself,
except that i386, alone of the archs, uses something other than user_mode().
Some notes on the interrupt handling in the drivers:
(*) input_dev() is now gone entirely. The regs pointer is no longer stored in
the input_dev struct.
(*) finish_unlinks() in drivers/usb/host/ohci-q.c needs checking. It does
something different depending on whether it's been supplied with a regs
pointer or not.
(*) Various IRQ handler function pointers have been moved to type
irq_handler_t.
Signed-Off-By: David Howells <dhowells@redhat.com>
(cherry picked from 1b16e7ac850969f38b375e511e3fa2f474a33867 commit)
2006-10-05 13:55:46 +00:00
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irqreturn_t snd_cs4231_interrupt(int irq, void *dev_id);
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2005-04-16 22:20:36 +00:00
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2005-11-17 13:30:42 +00:00
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const char *snd_cs4231_chip_id(struct snd_cs4231 *chip);
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2005-04-16 22:20:36 +00:00
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2005-11-17 13:30:42 +00:00
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int snd_cs4231_create(struct snd_card *card,
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2005-04-16 22:20:36 +00:00
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unsigned long port,
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unsigned long cport,
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int irq, int dma1, int dma2,
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unsigned short hardware,
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unsigned short hwshare,
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2005-11-17 13:30:42 +00:00
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struct snd_cs4231 ** rchip);
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int snd_cs4231_pcm(struct snd_cs4231 * chip, int device, struct snd_pcm **rpcm);
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int snd_cs4231_timer(struct snd_cs4231 * chip, int device, struct snd_timer **rtimer);
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int snd_cs4231_mixer(struct snd_cs4231 * chip);
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2005-04-16 22:20:36 +00:00
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2005-11-17 13:30:42 +00:00
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int snd_cs4236_create(struct snd_card *card,
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2005-04-16 22:20:36 +00:00
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unsigned long port,
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unsigned long cport,
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int irq, int dma1, int dma2,
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unsigned short hardware,
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unsigned short hwshare,
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2005-11-17 13:30:42 +00:00
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struct snd_cs4231 ** rchip);
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int snd_cs4236_pcm(struct snd_cs4231 * chip, int device, struct snd_pcm **rpcm);
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int snd_cs4236_mixer(struct snd_cs4231 * chip);
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2005-04-16 22:20:36 +00:00
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/*
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* mixer library
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*/
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#define CS4231_SINGLE(xname, xindex, reg, shift, mask, invert) \
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{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
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.info = snd_cs4231_info_single, \
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.get = snd_cs4231_get_single, .put = snd_cs4231_put_single, \
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.private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) }
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2005-11-17 13:30:42 +00:00
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int snd_cs4231_info_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo);
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int snd_cs4231_get_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
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int snd_cs4231_put_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
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2005-04-16 22:20:36 +00:00
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#define CS4231_DOUBLE(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert) \
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{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
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|
.info = snd_cs4231_info_double, \
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|
.get = snd_cs4231_get_double, .put = snd_cs4231_put_double, \
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|
.private_value = left_reg | (right_reg << 8) | (shift_left << 16) | (shift_right << 19) | (mask << 24) | (invert << 22) }
|
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|
2005-11-17 13:30:42 +00:00
|
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|
int snd_cs4231_info_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo);
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|
int snd_cs4231_get_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
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int snd_cs4231_put_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
|
2005-04-16 22:20:36 +00:00
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#endif /* __SOUND_CS4231_H */
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