2009-06-05 12:42:42 +00:00
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/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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*/
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#include <linux/console.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 08:04:11 +00:00
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#include <linux/slab.h>
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2009-06-05 12:42:42 +00:00
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#include <drm/drmP.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/radeon_drm.h>
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2009-09-21 04:33:58 +00:00
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#include <linux/vgaarb.h>
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2010-02-01 05:38:10 +00:00
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#include <linux/vga_switcheroo.h>
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2011-08-08 16:21:16 +00:00
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#include <linux/efi.h>
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2009-06-05 12:42:42 +00:00
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#include "radeon_reg.h"
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#include "radeon.h"
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#include "atom.h"
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2010-04-12 20:21:53 +00:00
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static const char radeon_family_name[][16] = {
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"R100",
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"RV100",
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"RS100",
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"RV200",
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"RS200",
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"R200",
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"RV250",
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"RS300",
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"RV280",
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"R300",
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"R350",
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"RV350",
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"RV380",
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"R420",
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"R423",
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"RV410",
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"RS400",
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"RS480",
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"RS600",
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"RS690",
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"RS740",
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"RV515",
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"R520",
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"RV530",
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"RV560",
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"RV570",
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"R580",
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"R600",
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"RV610",
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"RV630",
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"RV670",
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"RV620",
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"RV635",
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"RS780",
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"RS880",
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"RV770",
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"RV730",
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"RV710",
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"RV740",
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"CEDAR",
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"REDWOOD",
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"JUNIPER",
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"CYPRESS",
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"HEMLOCK",
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2010-12-03 20:34:16 +00:00
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"PALM",
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2011-05-31 19:42:46 +00:00
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"SUMO",
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"SUMO2",
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2011-01-07 02:19:12 +00:00
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"BARTS",
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"TURKS",
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"CAICOS",
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2011-03-03 01:07:27 +00:00
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"CAYMAN",
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2010-04-12 20:21:53 +00:00
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"LAST",
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};
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2009-06-23 14:12:54 +00:00
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/*
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* Clear GPU surface registers.
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*/
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2009-09-08 00:10:24 +00:00
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void radeon_surface_init(struct radeon_device *rdev)
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2009-06-23 14:12:54 +00:00
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{
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/* FIXME: check this out */
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if (rdev->family < CHIP_R600) {
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int i;
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2009-12-09 04:15:38 +00:00
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for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
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if (rdev->surface_regs[i].bo)
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radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
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else
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radeon_clear_surface_reg(rdev, i);
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2009-06-23 14:12:54 +00:00
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}
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2009-06-23 23:48:08 +00:00
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/* enable surfaces */
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WREG32(RADEON_SURFACE_CNTL, 0);
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2009-06-23 14:12:54 +00:00
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}
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}
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2009-06-05 12:42:42 +00:00
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/*
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* GPU scratch registers helpers function.
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*/
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2009-09-08 00:10:24 +00:00
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void radeon_scratch_init(struct radeon_device *rdev)
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2009-06-05 12:42:42 +00:00
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{
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int i;
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/* FIXME: check this out */
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if (rdev->family < CHIP_R300) {
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rdev->scratch.num_reg = 5;
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} else {
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rdev->scratch.num_reg = 7;
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}
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2010-08-27 22:25:25 +00:00
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rdev->scratch.reg_base = RADEON_SCRATCH_REG0;
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2009-06-05 12:42:42 +00:00
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for (i = 0; i < rdev->scratch.num_reg; i++) {
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rdev->scratch.free[i] = true;
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2010-08-27 22:25:25 +00:00
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rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
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2009-06-05 12:42:42 +00:00
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}
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}
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int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
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{
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int i;
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for (i = 0; i < rdev->scratch.num_reg; i++) {
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if (rdev->scratch.free[i]) {
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rdev->scratch.free[i] = false;
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*reg = rdev->scratch.reg[i];
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return 0;
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}
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}
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return -EINVAL;
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}
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void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
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{
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int i;
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for (i = 0; i < rdev->scratch.num_reg; i++) {
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if (rdev->scratch.reg[i] == reg) {
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rdev->scratch.free[i] = true;
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return;
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}
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}
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}
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2010-08-27 22:25:25 +00:00
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void radeon_wb_disable(struct radeon_device *rdev)
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{
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int r;
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if (rdev->wb.wb_obj) {
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r = radeon_bo_reserve(rdev->wb.wb_obj, false);
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if (unlikely(r != 0))
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return;
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radeon_bo_kunmap(rdev->wb.wb_obj);
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radeon_bo_unpin(rdev->wb.wb_obj);
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radeon_bo_unreserve(rdev->wb.wb_obj);
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}
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rdev->wb.enabled = false;
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}
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void radeon_wb_fini(struct radeon_device *rdev)
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{
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radeon_wb_disable(rdev);
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if (rdev->wb.wb_obj) {
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radeon_bo_unref(&rdev->wb.wb_obj);
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rdev->wb.wb = NULL;
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rdev->wb.wb_obj = NULL;
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}
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}
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int radeon_wb_init(struct radeon_device *rdev)
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{
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int r;
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if (rdev->wb.wb_obj == NULL) {
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2011-02-18 16:59:16 +00:00
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r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
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2010-08-27 22:25:25 +00:00
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RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj);
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if (r) {
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dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
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return r;
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}
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}
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r = radeon_bo_reserve(rdev->wb.wb_obj, false);
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if (unlikely(r != 0)) {
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radeon_wb_fini(rdev);
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return r;
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}
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r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
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&rdev->wb.gpu_addr);
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if (r) {
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radeon_bo_unreserve(rdev->wb.wb_obj);
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dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
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radeon_wb_fini(rdev);
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return r;
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}
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r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
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radeon_bo_unreserve(rdev->wb.wb_obj);
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if (r) {
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dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
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radeon_wb_fini(rdev);
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return r;
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}
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2011-06-13 22:02:51 +00:00
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/* clear wb memory */
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memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE);
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2010-09-04 09:04:34 +00:00
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/* disable event_write fences */
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rdev->wb.use_event = false;
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2010-08-27 22:25:25 +00:00
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/* disabled via module param */
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if (radeon_no_wb == 1)
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rdev->wb.enabled = false;
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else {
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/* often unreliable on AGP */
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if (rdev->flags & RADEON_IS_AGP) {
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rdev->wb.enabled = false;
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2010-09-04 09:04:34 +00:00
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} else {
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2010-08-27 22:25:25 +00:00
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rdev->wb.enabled = true;
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2010-09-04 09:04:34 +00:00
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/* event_write fences are only available on r600+ */
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if (rdev->family >= CHIP_R600)
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rdev->wb.use_event = true;
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}
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2010-08-27 22:25:25 +00:00
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}
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2011-01-07 02:19:27 +00:00
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/* always use writeback/events on NI */
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if (ASIC_IS_DCE5(rdev)) {
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rdev->wb.enabled = true;
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rdev->wb.use_event = true;
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}
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2010-08-27 22:25:25 +00:00
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dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis");
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return 0;
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}
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drm/radeon/kms: simplify memory controller setup V2
Get rid of _location and use _start/_end also simplify the
computation of vram_start|end & gtt_start|end. For R1XX-R2XX
we place VRAM at the same address of PCI aperture, those GPU
shouldn't have much memory and seems to behave better when
setup that way. For R3XX and newer we place VRAM at 0. For
R6XX-R7XX AGP we place VRAM before or after AGP aperture this
might limit to limit the VRAM size but it's very unlikely.
For IGP we don't change the VRAM placement.
Tested on (compiz,quake3,suspend/resume):
PCI/PCIE:RV280,R420,RV515,RV570,RV610,RV710
AGP:RV100,RV280,R420,RV350,RV620(RPB*),RV730
IGP:RS480(RPB*),RS690,RS780(RPB*),RS880
RPB: resume previously broken
V2 correct commit message to reflect more accurately the bug
and move VRAM placement to 0 for most of the GPU to avoid
limiting VRAM.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-02-17 21:54:29 +00:00
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/**
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* radeon_vram_location - try to find VRAM location
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* @rdev: radeon device structure holding all necessary informations
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* @mc: memory controller structure holding memory informations
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* @base: base address at which to put VRAM
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*
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* Function will place try to place VRAM at base address provided
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* as parameter (which is so far either PCI aperture address or
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* for IGP TOM base address).
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*
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* If there is not enough space to fit the unvisible VRAM in the 32bits
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* address space then we limit the VRAM size to the aperture.
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*
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* If we are using AGP and if the AGP aperture doesn't allow us to have
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* room for all the VRAM than we restrict the VRAM to the PCI aperture
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* size and print a warning.
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*
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* This function will never fails, worst case are limiting VRAM.
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*
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* Note: GTT start, end, size should be initialized before calling this
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* function on AGP platform.
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*
|
2011-03-31 01:57:33 +00:00
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* Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
|
drm/radeon/kms: simplify memory controller setup V2
Get rid of _location and use _start/_end also simplify the
computation of vram_start|end & gtt_start|end. For R1XX-R2XX
we place VRAM at the same address of PCI aperture, those GPU
shouldn't have much memory and seems to behave better when
setup that way. For R3XX and newer we place VRAM at 0. For
R6XX-R7XX AGP we place VRAM before or after AGP aperture this
might limit to limit the VRAM size but it's very unlikely.
For IGP we don't change the VRAM placement.
Tested on (compiz,quake3,suspend/resume):
PCI/PCIE:RV280,R420,RV515,RV570,RV610,RV710
AGP:RV100,RV280,R420,RV350,RV620(RPB*),RV730
IGP:RS480(RPB*),RS690,RS780(RPB*),RS880
RPB: resume previously broken
V2 correct commit message to reflect more accurately the bug
and move VRAM placement to 0 for most of the GPU to avoid
limiting VRAM.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-02-17 21:54:29 +00:00
|
|
|
* this shouldn't be a problem as we are using the PCI aperture as a reference.
|
|
|
|
* Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
|
|
|
|
* not IGP.
|
|
|
|
*
|
|
|
|
* Note: we use mc_vram_size as on some board we need to program the mc to
|
|
|
|
* cover the whole aperture even if VRAM size is inferior to aperture size
|
|
|
|
* Novell bug 204882 + along with lots of ubuntu ones
|
|
|
|
*
|
|
|
|
* Note: when limiting vram it's safe to overwritte real_vram_size because
|
|
|
|
* we are not in case where real_vram_size is inferior to mc_vram_size (ie
|
|
|
|
* note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
|
|
|
|
* ones)
|
|
|
|
*
|
|
|
|
* Note: IGP TOM addr should be the same as the aperture addr, we don't
|
|
|
|
* explicitly check for that thought.
|
|
|
|
*
|
|
|
|
* FIXME: when reducing VRAM size align new size on power of 2.
|
2009-06-05 12:42:42 +00:00
|
|
|
*/
|
drm/radeon/kms: simplify memory controller setup V2
Get rid of _location and use _start/_end also simplify the
computation of vram_start|end & gtt_start|end. For R1XX-R2XX
we place VRAM at the same address of PCI aperture, those GPU
shouldn't have much memory and seems to behave better when
setup that way. For R3XX and newer we place VRAM at 0. For
R6XX-R7XX AGP we place VRAM before or after AGP aperture this
might limit to limit the VRAM size but it's very unlikely.
For IGP we don't change the VRAM placement.
Tested on (compiz,quake3,suspend/resume):
PCI/PCIE:RV280,R420,RV515,RV570,RV610,RV710
AGP:RV100,RV280,R420,RV350,RV620(RPB*),RV730
IGP:RS480(RPB*),RS690,RS780(RPB*),RS880
RPB: resume previously broken
V2 correct commit message to reflect more accurately the bug
and move VRAM placement to 0 for most of the GPU to avoid
limiting VRAM.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-02-17 21:54:29 +00:00
|
|
|
void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
|
2009-06-05 12:42:42 +00:00
|
|
|
{
|
drm/radeon/kms: simplify memory controller setup V2
Get rid of _location and use _start/_end also simplify the
computation of vram_start|end & gtt_start|end. For R1XX-R2XX
we place VRAM at the same address of PCI aperture, those GPU
shouldn't have much memory and seems to behave better when
setup that way. For R3XX and newer we place VRAM at 0. For
R6XX-R7XX AGP we place VRAM before or after AGP aperture this
might limit to limit the VRAM size but it's very unlikely.
For IGP we don't change the VRAM placement.
Tested on (compiz,quake3,suspend/resume):
PCI/PCIE:RV280,R420,RV515,RV570,RV610,RV710
AGP:RV100,RV280,R420,RV350,RV620(RPB*),RV730
IGP:RS480(RPB*),RS690,RS780(RPB*),RS880
RPB: resume previously broken
V2 correct commit message to reflect more accurately the bug
and move VRAM placement to 0 for most of the GPU to avoid
limiting VRAM.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-02-17 21:54:29 +00:00
|
|
|
mc->vram_start = base;
|
|
|
|
if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) {
|
|
|
|
dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
|
|
|
|
mc->real_vram_size = mc->aper_size;
|
|
|
|
mc->mc_vram_size = mc->aper_size;
|
|
|
|
}
|
|
|
|
mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
|
2010-08-16 15:54:36 +00:00
|
|
|
if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) {
|
drm/radeon/kms: simplify memory controller setup V2
Get rid of _location and use _start/_end also simplify the
computation of vram_start|end & gtt_start|end. For R1XX-R2XX
we place VRAM at the same address of PCI aperture, those GPU
shouldn't have much memory and seems to behave better when
setup that way. For R3XX and newer we place VRAM at 0. For
R6XX-R7XX AGP we place VRAM before or after AGP aperture this
might limit to limit the VRAM size but it's very unlikely.
For IGP we don't change the VRAM placement.
Tested on (compiz,quake3,suspend/resume):
PCI/PCIE:RV280,R420,RV515,RV570,RV610,RV710
AGP:RV100,RV280,R420,RV350,RV620(RPB*),RV730
IGP:RS480(RPB*),RS690,RS780(RPB*),RS880
RPB: resume previously broken
V2 correct commit message to reflect more accurately the bug
and move VRAM placement to 0 for most of the GPU to avoid
limiting VRAM.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-02-17 21:54:29 +00:00
|
|
|
dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
|
|
|
|
mc->real_vram_size = mc->aper_size;
|
|
|
|
mc->mc_vram_size = mc->aper_size;
|
|
|
|
}
|
|
|
|
mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
|
2011-08-19 15:24:18 +00:00
|
|
|
if (radeon_vram_limit && radeon_vram_limit < mc->real_vram_size)
|
|
|
|
mc->real_vram_size = radeon_vram_limit;
|
2010-12-03 19:37:21 +00:00
|
|
|
dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
|
drm/radeon/kms: simplify memory controller setup V2
Get rid of _location and use _start/_end also simplify the
computation of vram_start|end & gtt_start|end. For R1XX-R2XX
we place VRAM at the same address of PCI aperture, those GPU
shouldn't have much memory and seems to behave better when
setup that way. For R3XX and newer we place VRAM at 0. For
R6XX-R7XX AGP we place VRAM before or after AGP aperture this
might limit to limit the VRAM size but it's very unlikely.
For IGP we don't change the VRAM placement.
Tested on (compiz,quake3,suspend/resume):
PCI/PCIE:RV280,R420,RV515,RV570,RV610,RV710
AGP:RV100,RV280,R420,RV350,RV620(RPB*),RV730
IGP:RS480(RPB*),RS690,RS780(RPB*),RS880
RPB: resume previously broken
V2 correct commit message to reflect more accurately the bug
and move VRAM placement to 0 for most of the GPU to avoid
limiting VRAM.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-02-17 21:54:29 +00:00
|
|
|
mc->mc_vram_size >> 20, mc->vram_start,
|
|
|
|
mc->vram_end, mc->real_vram_size >> 20);
|
|
|
|
}
|
2009-06-05 12:42:42 +00:00
|
|
|
|
drm/radeon/kms: simplify memory controller setup V2
Get rid of _location and use _start/_end also simplify the
computation of vram_start|end & gtt_start|end. For R1XX-R2XX
we place VRAM at the same address of PCI aperture, those GPU
shouldn't have much memory and seems to behave better when
setup that way. For R3XX and newer we place VRAM at 0. For
R6XX-R7XX AGP we place VRAM before or after AGP aperture this
might limit to limit the VRAM size but it's very unlikely.
For IGP we don't change the VRAM placement.
Tested on (compiz,quake3,suspend/resume):
PCI/PCIE:RV280,R420,RV515,RV570,RV610,RV710
AGP:RV100,RV280,R420,RV350,RV620(RPB*),RV730
IGP:RS480(RPB*),RS690,RS780(RPB*),RS880
RPB: resume previously broken
V2 correct commit message to reflect more accurately the bug
and move VRAM placement to 0 for most of the GPU to avoid
limiting VRAM.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-02-17 21:54:29 +00:00
|
|
|
/**
|
|
|
|
* radeon_gtt_location - try to find GTT location
|
|
|
|
* @rdev: radeon device structure holding all necessary informations
|
|
|
|
* @mc: memory controller structure holding memory informations
|
|
|
|
*
|
|
|
|
* Function will place try to place GTT before or after VRAM.
|
|
|
|
*
|
|
|
|
* If GTT size is bigger than space left then we ajust GTT size.
|
|
|
|
* Thus function will never fails.
|
|
|
|
*
|
|
|
|
* FIXME: when reducing GTT size align new size on power of 2.
|
|
|
|
*/
|
|
|
|
void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
|
|
|
|
{
|
|
|
|
u64 size_af, size_bf;
|
|
|
|
|
2010-07-15 14:51:10 +00:00
|
|
|
size_af = ((0xFFFFFFFF - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
|
|
|
|
size_bf = mc->vram_start & ~mc->gtt_base_align;
|
drm/radeon/kms: simplify memory controller setup V2
Get rid of _location and use _start/_end also simplify the
computation of vram_start|end & gtt_start|end. For R1XX-R2XX
we place VRAM at the same address of PCI aperture, those GPU
shouldn't have much memory and seems to behave better when
setup that way. For R3XX and newer we place VRAM at 0. For
R6XX-R7XX AGP we place VRAM before or after AGP aperture this
might limit to limit the VRAM size but it's very unlikely.
For IGP we don't change the VRAM placement.
Tested on (compiz,quake3,suspend/resume):
PCI/PCIE:RV280,R420,RV515,RV570,RV610,RV710
AGP:RV100,RV280,R420,RV350,RV620(RPB*),RV730
IGP:RS480(RPB*),RS690,RS780(RPB*),RS880
RPB: resume previously broken
V2 correct commit message to reflect more accurately the bug
and move VRAM placement to 0 for most of the GPU to avoid
limiting VRAM.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-02-17 21:54:29 +00:00
|
|
|
if (size_bf > size_af) {
|
|
|
|
if (mc->gtt_size > size_bf) {
|
|
|
|
dev_warn(rdev->dev, "limiting GTT\n");
|
|
|
|
mc->gtt_size = size_bf;
|
2009-06-05 12:42:42 +00:00
|
|
|
}
|
2010-07-15 14:51:10 +00:00
|
|
|
mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
|
2009-06-05 12:42:42 +00:00
|
|
|
} else {
|
drm/radeon/kms: simplify memory controller setup V2
Get rid of _location and use _start/_end also simplify the
computation of vram_start|end & gtt_start|end. For R1XX-R2XX
we place VRAM at the same address of PCI aperture, those GPU
shouldn't have much memory and seems to behave better when
setup that way. For R3XX and newer we place VRAM at 0. For
R6XX-R7XX AGP we place VRAM before or after AGP aperture this
might limit to limit the VRAM size but it's very unlikely.
For IGP we don't change the VRAM placement.
Tested on (compiz,quake3,suspend/resume):
PCI/PCIE:RV280,R420,RV515,RV570,RV610,RV710
AGP:RV100,RV280,R420,RV350,RV620(RPB*),RV730
IGP:RS480(RPB*),RS690,RS780(RPB*),RS880
RPB: resume previously broken
V2 correct commit message to reflect more accurately the bug
and move VRAM placement to 0 for most of the GPU to avoid
limiting VRAM.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-02-17 21:54:29 +00:00
|
|
|
if (mc->gtt_size > size_af) {
|
|
|
|
dev_warn(rdev->dev, "limiting GTT\n");
|
|
|
|
mc->gtt_size = size_af;
|
|
|
|
}
|
2010-07-15 14:51:10 +00:00
|
|
|
mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
|
2009-06-05 12:42:42 +00:00
|
|
|
}
|
drm/radeon/kms: simplify memory controller setup V2
Get rid of _location and use _start/_end also simplify the
computation of vram_start|end & gtt_start|end. For R1XX-R2XX
we place VRAM at the same address of PCI aperture, those GPU
shouldn't have much memory and seems to behave better when
setup that way. For R3XX and newer we place VRAM at 0. For
R6XX-R7XX AGP we place VRAM before or after AGP aperture this
might limit to limit the VRAM size but it's very unlikely.
For IGP we don't change the VRAM placement.
Tested on (compiz,quake3,suspend/resume):
PCI/PCIE:RV280,R420,RV515,RV570,RV610,RV710
AGP:RV100,RV280,R420,RV350,RV620(RPB*),RV730
IGP:RS480(RPB*),RS690,RS780(RPB*),RS880
RPB: resume previously broken
V2 correct commit message to reflect more accurately the bug
and move VRAM placement to 0 for most of the GPU to avoid
limiting VRAM.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-02-17 21:54:29 +00:00
|
|
|
mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
|
2010-12-03 19:37:21 +00:00
|
|
|
dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
|
drm/radeon/kms: simplify memory controller setup V2
Get rid of _location and use _start/_end also simplify the
computation of vram_start|end & gtt_start|end. For R1XX-R2XX
we place VRAM at the same address of PCI aperture, those GPU
shouldn't have much memory and seems to behave better when
setup that way. For R3XX and newer we place VRAM at 0. For
R6XX-R7XX AGP we place VRAM before or after AGP aperture this
might limit to limit the VRAM size but it's very unlikely.
For IGP we don't change the VRAM placement.
Tested on (compiz,quake3,suspend/resume):
PCI/PCIE:RV280,R420,RV515,RV570,RV610,RV710
AGP:RV100,RV280,R420,RV350,RV620(RPB*),RV730
IGP:RS480(RPB*),RS690,RS780(RPB*),RS880
RPB: resume previously broken
V2 correct commit message to reflect more accurately the bug
and move VRAM placement to 0 for most of the GPU to avoid
limiting VRAM.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-02-17 21:54:29 +00:00
|
|
|
mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
|
2009-06-05 12:42:42 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* GPU helpers function.
|
|
|
|
*/
|
2009-09-11 13:35:22 +00:00
|
|
|
bool radeon_card_posted(struct radeon_device *rdev)
|
2009-06-05 12:42:42 +00:00
|
|
|
{
|
|
|
|
uint32_t reg;
|
|
|
|
|
2011-08-08 16:21:16 +00:00
|
|
|
if (efi_enabled && rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE)
|
|
|
|
return false;
|
|
|
|
|
2009-06-05 12:42:42 +00:00
|
|
|
/* first check CRTCs */
|
2010-11-22 22:56:28 +00:00
|
|
|
if (ASIC_IS_DCE41(rdev)) {
|
|
|
|
reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
|
|
|
|
RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
|
|
|
|
if (reg & EVERGREEN_CRTC_MASTER_EN)
|
|
|
|
return true;
|
|
|
|
} else if (ASIC_IS_DCE4(rdev)) {
|
2010-01-12 22:54:34 +00:00
|
|
|
reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
|
|
|
|
RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
|
|
|
|
RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
|
|
|
|
RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
|
|
|
|
RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
|
|
|
|
RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
|
|
|
|
if (reg & EVERGREEN_CRTC_MASTER_EN)
|
|
|
|
return true;
|
|
|
|
} else if (ASIC_IS_AVIVO(rdev)) {
|
2009-06-05 12:42:42 +00:00
|
|
|
reg = RREG32(AVIVO_D1CRTC_CONTROL) |
|
|
|
|
RREG32(AVIVO_D2CRTC_CONTROL);
|
|
|
|
if (reg & AVIVO_CRTC_EN) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
reg = RREG32(RADEON_CRTC_GEN_CNTL) |
|
|
|
|
RREG32(RADEON_CRTC2_GEN_CNTL);
|
|
|
|
if (reg & RADEON_CRTC_EN) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* then check MEM_SIZE, in case the crtcs are off */
|
|
|
|
if (rdev->family >= CHIP_R600)
|
|
|
|
reg = RREG32(R600_CONFIG_MEMSIZE);
|
|
|
|
else
|
|
|
|
reg = RREG32(RADEON_CONFIG_MEMSIZE);
|
|
|
|
|
|
|
|
if (reg)
|
|
|
|
return true;
|
|
|
|
|
|
|
|
return false;
|
|
|
|
|
|
|
|
}
|
|
|
|
|
2010-03-17 00:54:38 +00:00
|
|
|
void radeon_update_bandwidth_info(struct radeon_device *rdev)
|
|
|
|
{
|
|
|
|
fixed20_12 a;
|
2010-08-10 16:33:20 +00:00
|
|
|
u32 sclk = rdev->pm.current_sclk;
|
|
|
|
u32 mclk = rdev->pm.current_mclk;
|
2010-03-17 00:54:38 +00:00
|
|
|
|
2010-08-10 16:33:20 +00:00
|
|
|
/* sclk/mclk in Mhz */
|
|
|
|
a.full = dfixed_const(100);
|
|
|
|
rdev->pm.sclk.full = dfixed_const(sclk);
|
|
|
|
rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
|
|
|
|
rdev->pm.mclk.full = dfixed_const(mclk);
|
|
|
|
rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
|
2010-03-17 00:54:38 +00:00
|
|
|
|
2010-08-10 16:33:20 +00:00
|
|
|
if (rdev->flags & RADEON_IS_IGP) {
|
2010-04-28 01:46:42 +00:00
|
|
|
a.full = dfixed_const(16);
|
2010-03-17 00:54:38 +00:00
|
|
|
/* core_bandwidth = sclk(Mhz) * 16 */
|
2010-04-28 01:46:42 +00:00
|
|
|
rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
|
2010-03-17 00:54:38 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-12-01 04:06:31 +00:00
|
|
|
bool radeon_boot_test_post_card(struct radeon_device *rdev)
|
|
|
|
{
|
|
|
|
if (radeon_card_posted(rdev))
|
|
|
|
return true;
|
|
|
|
|
|
|
|
if (rdev->bios) {
|
|
|
|
DRM_INFO("GPU not posted. posting now...\n");
|
|
|
|
if (rdev->is_atom_bios)
|
|
|
|
atom_asic_init(rdev->mode_info.atom_context);
|
|
|
|
else
|
|
|
|
radeon_combios_asic_init(rdev->ddev);
|
|
|
|
return true;
|
|
|
|
} else {
|
|
|
|
dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-09-08 00:10:24 +00:00
|
|
|
int radeon_dummy_page_init(struct radeon_device *rdev)
|
|
|
|
{
|
2010-02-05 06:00:07 +00:00
|
|
|
if (rdev->dummy_page.page)
|
|
|
|
return 0;
|
2009-09-08 00:10:24 +00:00
|
|
|
rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
|
|
|
|
if (rdev->dummy_page.page == NULL)
|
|
|
|
return -ENOMEM;
|
|
|
|
rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
|
|
|
|
0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
|
2010-08-10 04:48:58 +00:00
|
|
|
if (pci_dma_mapping_error(rdev->pdev, rdev->dummy_page.addr)) {
|
|
|
|
dev_err(&rdev->pdev->dev, "Failed to DMA MAP the dummy page\n");
|
2009-09-08 00:10:24 +00:00
|
|
|
__free_page(rdev->dummy_page.page);
|
|
|
|
rdev->dummy_page.page = NULL;
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void radeon_dummy_page_fini(struct radeon_device *rdev)
|
|
|
|
{
|
|
|
|
if (rdev->dummy_page.page == NULL)
|
|
|
|
return;
|
|
|
|
pci_unmap_page(rdev->pdev, rdev->dummy_page.addr,
|
|
|
|
PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
|
|
|
|
__free_page(rdev->dummy_page.page);
|
|
|
|
rdev->dummy_page.page = NULL;
|
|
|
|
}
|
|
|
|
|
2009-06-05 12:42:42 +00:00
|
|
|
|
|
|
|
/* ATOM accessor methods */
|
|
|
|
static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
|
|
|
|
{
|
|
|
|
struct radeon_device *rdev = info->dev->dev_private;
|
|
|
|
uint32_t r;
|
|
|
|
|
|
|
|
r = rdev->pll_rreg(rdev, reg);
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
|
|
|
|
{
|
|
|
|
struct radeon_device *rdev = info->dev->dev_private;
|
|
|
|
|
|
|
|
rdev->pll_wreg(rdev, reg, val);
|
|
|
|
}
|
|
|
|
|
|
|
|
static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
|
|
|
|
{
|
|
|
|
struct radeon_device *rdev = info->dev->dev_private;
|
|
|
|
uint32_t r;
|
|
|
|
|
|
|
|
r = rdev->mc_rreg(rdev, reg);
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
|
|
|
|
{
|
|
|
|
struct radeon_device *rdev = info->dev->dev_private;
|
|
|
|
|
|
|
|
rdev->mc_wreg(rdev, reg, val);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
|
|
|
|
{
|
|
|
|
struct radeon_device *rdev = info->dev->dev_private;
|
|
|
|
|
|
|
|
WREG32(reg*4, val);
|
|
|
|
}
|
|
|
|
|
|
|
|
static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
|
|
|
|
{
|
|
|
|
struct radeon_device *rdev = info->dev->dev_private;
|
|
|
|
uint32_t r;
|
|
|
|
|
|
|
|
r = RREG32(reg*4);
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
2010-06-30 15:52:50 +00:00
|
|
|
static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
|
|
|
|
{
|
|
|
|
struct radeon_device *rdev = info->dev->dev_private;
|
|
|
|
|
|
|
|
WREG32_IO(reg*4, val);
|
|
|
|
}
|
|
|
|
|
|
|
|
static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
|
|
|
|
{
|
|
|
|
struct radeon_device *rdev = info->dev->dev_private;
|
|
|
|
uint32_t r;
|
|
|
|
|
|
|
|
r = RREG32_IO(reg*4);
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
2009-06-05 12:42:42 +00:00
|
|
|
int radeon_atombios_init(struct radeon_device *rdev)
|
|
|
|
{
|
2009-10-27 19:08:01 +00:00
|
|
|
struct card_info *atom_card_info =
|
|
|
|
kzalloc(sizeof(struct card_info), GFP_KERNEL);
|
|
|
|
|
|
|
|
if (!atom_card_info)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
rdev->mode_info.atom_card_info = atom_card_info;
|
|
|
|
atom_card_info->dev = rdev->ddev;
|
|
|
|
atom_card_info->reg_read = cail_reg_read;
|
|
|
|
atom_card_info->reg_write = cail_reg_write;
|
2010-06-30 15:52:50 +00:00
|
|
|
/* needed for iio ops */
|
|
|
|
if (rdev->rio_mem) {
|
|
|
|
atom_card_info->ioreg_read = cail_ioreg_read;
|
|
|
|
atom_card_info->ioreg_write = cail_ioreg_write;
|
|
|
|
} else {
|
|
|
|
DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
|
|
|
|
atom_card_info->ioreg_read = cail_reg_read;
|
|
|
|
atom_card_info->ioreg_write = cail_reg_write;
|
|
|
|
}
|
2009-10-27 19:08:01 +00:00
|
|
|
atom_card_info->mc_read = cail_mc_read;
|
|
|
|
atom_card_info->mc_write = cail_mc_write;
|
|
|
|
atom_card_info->pll_read = cail_pll_read;
|
|
|
|
atom_card_info->pll_write = cail_pll_write;
|
|
|
|
|
|
|
|
rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
|
2009-12-16 23:00:46 +00:00
|
|
|
mutex_init(&rdev->mode_info.atom_context->mutex);
|
2009-06-05 12:42:42 +00:00
|
|
|
radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
|
2009-11-16 20:29:46 +00:00
|
|
|
atom_allocate_fb_scratch(rdev->mode_info.atom_context);
|
2009-06-05 12:42:42 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void radeon_atombios_fini(struct radeon_device *rdev)
|
|
|
|
{
|
2009-12-09 16:39:16 +00:00
|
|
|
if (rdev->mode_info.atom_context) {
|
|
|
|
kfree(rdev->mode_info.atom_context->scratch);
|
|
|
|
kfree(rdev->mode_info.atom_context);
|
|
|
|
}
|
2009-10-27 19:08:01 +00:00
|
|
|
kfree(rdev->mode_info.atom_card_info);
|
2009-06-05 12:42:42 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
int radeon_combios_init(struct radeon_device *rdev)
|
|
|
|
{
|
|
|
|
radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void radeon_combios_fini(struct radeon_device *rdev)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
2009-09-21 04:33:58 +00:00
|
|
|
/* if we get transitioned to only one device, tak VGA back */
|
|
|
|
static unsigned int radeon_vga_set_decode(void *cookie, bool state)
|
|
|
|
{
|
|
|
|
struct radeon_device *rdev = cookie;
|
|
|
|
radeon_vga_set_state(rdev, state);
|
|
|
|
if (state)
|
|
|
|
return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
|
|
|
|
VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
|
|
|
|
else
|
|
|
|
return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
|
|
|
|
}
|
2009-10-08 04:03:05 +00:00
|
|
|
|
2009-12-11 20:18:34 +00:00
|
|
|
void radeon_check_arguments(struct radeon_device *rdev)
|
|
|
|
{
|
|
|
|
/* vramlimit must be a power of two */
|
|
|
|
switch (radeon_vram_limit) {
|
|
|
|
case 0:
|
|
|
|
case 4:
|
|
|
|
case 8:
|
|
|
|
case 16:
|
|
|
|
case 32:
|
|
|
|
case 64:
|
|
|
|
case 128:
|
|
|
|
case 256:
|
|
|
|
case 512:
|
|
|
|
case 1024:
|
|
|
|
case 2048:
|
|
|
|
case 4096:
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
|
|
|
|
radeon_vram_limit);
|
|
|
|
radeon_vram_limit = 0;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
radeon_vram_limit = radeon_vram_limit << 20;
|
|
|
|
/* gtt size must be power of two and greater or equal to 32M */
|
|
|
|
switch (radeon_gart_size) {
|
|
|
|
case 4:
|
|
|
|
case 8:
|
|
|
|
case 16:
|
|
|
|
dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n",
|
|
|
|
radeon_gart_size);
|
|
|
|
radeon_gart_size = 512;
|
|
|
|
break;
|
|
|
|
case 32:
|
|
|
|
case 64:
|
|
|
|
case 128:
|
|
|
|
case 256:
|
|
|
|
case 512:
|
|
|
|
case 1024:
|
|
|
|
case 2048:
|
|
|
|
case 4096:
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
|
|
|
|
radeon_gart_size);
|
|
|
|
radeon_gart_size = 512;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
|
|
|
|
/* AGP mode can only be -1, 1, 2, 4, 8 */
|
|
|
|
switch (radeon_agpmode) {
|
|
|
|
case -1:
|
|
|
|
case 0:
|
|
|
|
case 1:
|
|
|
|
case 2:
|
|
|
|
case 4:
|
|
|
|
case 8:
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
|
|
|
|
"-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
|
|
|
|
radeon_agpmode = 0;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-02-01 05:38:10 +00:00
|
|
|
static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = pci_get_drvdata(pdev);
|
|
|
|
pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
|
|
|
|
if (state == VGA_SWITCHEROO_ON) {
|
|
|
|
printk(KERN_INFO "radeon: switched on\n");
|
|
|
|
/* don't suspend or resume card normally */
|
2010-12-06 23:20:40 +00:00
|
|
|
dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
|
2010-02-01 05:38:10 +00:00
|
|
|
radeon_resume_kms(dev);
|
2010-12-06 23:20:40 +00:00
|
|
|
dev->switch_power_state = DRM_SWITCH_POWER_ON;
|
2010-05-31 23:09:06 +00:00
|
|
|
drm_kms_helper_poll_enable(dev);
|
2010-02-01 05:38:10 +00:00
|
|
|
} else {
|
|
|
|
printk(KERN_INFO "radeon: switched off\n");
|
2010-05-31 23:09:06 +00:00
|
|
|
drm_kms_helper_poll_disable(dev);
|
2010-12-06 23:20:40 +00:00
|
|
|
dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
|
2010-02-01 05:38:10 +00:00
|
|
|
radeon_suspend_kms(dev, pmm);
|
2010-12-06 23:20:40 +00:00
|
|
|
dev->switch_power_state = DRM_SWITCH_POWER_OFF;
|
2010-02-01 05:38:10 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool radeon_switcheroo_can_switch(struct pci_dev *pdev)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = pci_get_drvdata(pdev);
|
|
|
|
bool can_switch;
|
|
|
|
|
|
|
|
spin_lock(&dev->count_lock);
|
|
|
|
can_switch = (dev->open_count == 0);
|
|
|
|
spin_unlock(&dev->count_lock);
|
|
|
|
return can_switch;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2009-06-05 12:42:42 +00:00
|
|
|
int radeon_device_init(struct radeon_device *rdev,
|
|
|
|
struct drm_device *ddev,
|
|
|
|
struct pci_dev *pdev,
|
|
|
|
uint32_t flags)
|
|
|
|
{
|
2010-06-30 15:52:50 +00:00
|
|
|
int r, i;
|
2009-07-10 12:36:26 +00:00
|
|
|
int dma_bits;
|
2009-06-05 12:42:42 +00:00
|
|
|
|
|
|
|
rdev->shutdown = false;
|
2009-09-11 13:35:22 +00:00
|
|
|
rdev->dev = &pdev->dev;
|
2009-06-05 12:42:42 +00:00
|
|
|
rdev->ddev = ddev;
|
|
|
|
rdev->pdev = pdev;
|
|
|
|
rdev->flags = flags;
|
|
|
|
rdev->family = flags & RADEON_FAMILY_MASK;
|
|
|
|
rdev->is_atom_bios = false;
|
|
|
|
rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
|
|
|
|
rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
|
|
|
|
rdev->gpu_lockup = false;
|
2009-09-16 13:24:21 +00:00
|
|
|
rdev->accel_working = false;
|
2010-04-12 20:21:53 +00:00
|
|
|
|
2011-07-29 14:28:59 +00:00
|
|
|
DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n",
|
|
|
|
radeon_family_name[rdev->family], pdev->vendor, pdev->device,
|
|
|
|
pdev->subsystem_vendor, pdev->subsystem_device);
|
2010-04-12 20:21:53 +00:00
|
|
|
|
2009-06-05 12:42:42 +00:00
|
|
|
/* mutex initialization are all done here so we
|
|
|
|
* can recall function without having locking issues */
|
2011-11-10 17:57:26 +00:00
|
|
|
radeon_mutex_init(&rdev->cs_mutex);
|
2009-06-05 12:42:42 +00:00
|
|
|
mutex_init(&rdev->ib_pool.mutex);
|
|
|
|
mutex_init(&rdev->cp.mutex);
|
2009-12-23 08:23:21 +00:00
|
|
|
mutex_init(&rdev->dc_hw_i2c_mutex);
|
2009-12-01 18:43:46 +00:00
|
|
|
if (rdev->family >= CHIP_R600)
|
|
|
|
spin_lock_init(&rdev->ih.lock);
|
2009-11-20 13:29:23 +00:00
|
|
|
mutex_init(&rdev->gem.mutex);
|
2009-12-22 22:02:16 +00:00
|
|
|
mutex_init(&rdev->pm.mutex);
|
2010-04-26 19:52:20 +00:00
|
|
|
mutex_init(&rdev->vram_mutex);
|
2009-06-05 12:42:42 +00:00
|
|
|
rwlock_init(&rdev->fence_drv.lock);
|
2009-09-11 13:35:22 +00:00
|
|
|
INIT_LIST_HEAD(&rdev->gem.objects);
|
2010-01-07 23:22:47 +00:00
|
|
|
init_waitqueue_head(&rdev->irq.vblank_queue);
|
2010-04-22 16:52:11 +00:00
|
|
|
init_waitqueue_head(&rdev->irq.idle_queue);
|
2009-06-05 12:42:42 +00:00
|
|
|
|
2009-09-14 16:29:49 +00:00
|
|
|
/* Set asic functions */
|
|
|
|
r = radeon_asic_init(rdev);
|
2009-12-11 20:18:34 +00:00
|
|
|
if (r)
|
2009-09-14 16:29:49 +00:00
|
|
|
return r;
|
2009-12-11 20:18:34 +00:00
|
|
|
radeon_check_arguments(rdev);
|
2009-09-14 16:29:49 +00:00
|
|
|
|
2010-03-21 18:02:25 +00:00
|
|
|
/* all of the newer IGP chips have an internal gart
|
|
|
|
* However some rs4xx report as AGP, so remove that here.
|
|
|
|
*/
|
|
|
|
if ((rdev->family >= CHIP_RS400) &&
|
|
|
|
(rdev->flags & RADEON_IS_IGP)) {
|
|
|
|
rdev->flags &= ~RADEON_IS_AGP;
|
|
|
|
}
|
|
|
|
|
2009-11-30 16:47:59 +00:00
|
|
|
if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
|
2009-10-06 17:04:29 +00:00
|
|
|
radeon_agp_disable(rdev);
|
2009-06-05 12:42:42 +00:00
|
|
|
}
|
|
|
|
|
2009-07-10 12:36:26 +00:00
|
|
|
/* set DMA mask + need_dma32 flags.
|
|
|
|
* PCIE - can handle 40-bits.
|
2011-10-05 14:02:57 +00:00
|
|
|
* IGP - can handle 40-bits
|
2009-07-10 12:36:26 +00:00
|
|
|
* AGP - generally dma32 is safest
|
2011-10-05 14:02:57 +00:00
|
|
|
* PCI - dma32 for legacy pci gart, 40 bits on newer asics
|
2009-07-10 12:36:26 +00:00
|
|
|
*/
|
|
|
|
rdev->need_dma32 = false;
|
|
|
|
if (rdev->flags & RADEON_IS_AGP)
|
|
|
|
rdev->need_dma32 = true;
|
2011-10-05 14:02:57 +00:00
|
|
|
if ((rdev->flags & RADEON_IS_PCI) &&
|
|
|
|
(rdev->family < CHIP_RS400))
|
2009-07-10 12:36:26 +00:00
|
|
|
rdev->need_dma32 = true;
|
|
|
|
|
|
|
|
dma_bits = rdev->need_dma32 ? 32 : 40;
|
|
|
|
r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
|
2009-06-05 12:42:42 +00:00
|
|
|
if (r) {
|
2011-06-08 10:04:45 +00:00
|
|
|
rdev->need_dma32 = true;
|
2009-06-05 12:42:42 +00:00
|
|
|
printk(KERN_WARNING "radeon: No suitable DMA available.\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Registers mapping */
|
|
|
|
/* TODO: block userspace mapping of io register */
|
2010-05-27 19:40:24 +00:00
|
|
|
rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
|
|
|
|
rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
|
2009-06-05 12:42:42 +00:00
|
|
|
rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
|
|
|
|
if (rdev->rmmio == NULL) {
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
|
|
|
|
DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
|
|
|
|
|
2010-06-30 15:52:50 +00:00
|
|
|
/* io port mapping */
|
|
|
|
for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
|
|
|
|
if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) {
|
|
|
|
rdev->rio_mem_size = pci_resource_len(rdev->pdev, i);
|
|
|
|
rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (rdev->rio_mem == NULL)
|
|
|
|
DRM_ERROR("Unable to find PCI I/O BAR\n");
|
|
|
|
|
2009-09-21 04:33:58 +00:00
|
|
|
/* if we have > 1 VGA cards, then disable the radeon VGA resources */
|
2009-10-28 01:09:58 +00:00
|
|
|
/* this will fail for cards that aren't VGA class devices, just
|
|
|
|
* ignore it */
|
|
|
|
vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
|
2010-02-01 05:38:10 +00:00
|
|
|
vga_switcheroo_register_client(rdev->pdev,
|
|
|
|
radeon_switcheroo_set_state,
|
2010-12-06 22:57:57 +00:00
|
|
|
NULL,
|
2010-02-01 05:38:10 +00:00
|
|
|
radeon_switcheroo_can_switch);
|
2009-09-21 04:33:58 +00:00
|
|
|
|
2009-09-08 00:10:24 +00:00
|
|
|
r = radeon_init(rdev);
|
2009-10-06 17:04:29 +00:00
|
|
|
if (r)
|
2009-09-08 00:10:24 +00:00
|
|
|
return r;
|
|
|
|
|
2009-10-06 17:04:29 +00:00
|
|
|
if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
|
|
|
|
/* Acceleration not working on AGP card try again
|
|
|
|
* with fallback to PCI or PCIE GART
|
|
|
|
*/
|
2010-03-09 14:45:11 +00:00
|
|
|
radeon_asic_reset(rdev);
|
2009-10-06 17:04:29 +00:00
|
|
|
radeon_fini(rdev);
|
|
|
|
radeon_agp_disable(rdev);
|
|
|
|
r = radeon_init(rdev);
|
2009-09-14 16:29:49 +00:00
|
|
|
if (r)
|
|
|
|
return r;
|
2009-06-05 12:42:42 +00:00
|
|
|
}
|
2009-07-21 09:23:57 +00:00
|
|
|
if (radeon_testing) {
|
|
|
|
radeon_test_moves(rdev);
|
|
|
|
}
|
2009-06-05 12:42:42 +00:00
|
|
|
if (radeon_benchmarking) {
|
2011-10-13 03:29:39 +00:00
|
|
|
radeon_benchmark(rdev, radeon_benchmarking);
|
2009-06-05 12:42:42 +00:00
|
|
|
}
|
2009-09-10 19:46:48 +00:00
|
|
|
return 0;
|
2009-06-05 12:42:42 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void radeon_device_fini(struct radeon_device *rdev)
|
|
|
|
{
|
|
|
|
DRM_INFO("radeon: finishing device.\n");
|
|
|
|
rdev->shutdown = true;
|
2010-03-09 14:45:12 +00:00
|
|
|
/* evict vram memory */
|
|
|
|
radeon_bo_evict_vram(rdev);
|
2009-10-01 16:02:11 +00:00
|
|
|
radeon_fini(rdev);
|
2010-02-01 05:38:10 +00:00
|
|
|
vga_switcheroo_unregister_client(rdev->pdev);
|
2009-10-08 04:03:05 +00:00
|
|
|
vga_client_register(rdev->pdev, NULL, NULL, NULL);
|
2010-07-08 16:24:52 +00:00
|
|
|
if (rdev->rio_mem)
|
|
|
|
pci_iounmap(rdev->pdev, rdev->rio_mem);
|
2010-06-30 15:52:50 +00:00
|
|
|
rdev->rio_mem = NULL;
|
2009-06-05 12:42:42 +00:00
|
|
|
iounmap(rdev->rmmio);
|
|
|
|
rdev->rmmio = NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Suspend & resume.
|
|
|
|
*/
|
|
|
|
int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
|
|
|
|
{
|
2009-12-30 01:18:30 +00:00
|
|
|
struct radeon_device *rdev;
|
2009-06-05 12:42:42 +00:00
|
|
|
struct drm_crtc *crtc;
|
2010-06-02 16:08:41 +00:00
|
|
|
struct drm_connector *connector;
|
2009-11-20 13:29:23 +00:00
|
|
|
int r;
|
2009-06-05 12:42:42 +00:00
|
|
|
|
2009-12-30 01:18:30 +00:00
|
|
|
if (dev == NULL || dev->dev_private == NULL) {
|
2009-06-05 12:42:42 +00:00
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
if (state.event == PM_EVENT_PRETHAW) {
|
|
|
|
return 0;
|
|
|
|
}
|
2009-12-30 01:18:30 +00:00
|
|
|
rdev = dev->dev_private;
|
|
|
|
|
2010-12-06 23:20:40 +00:00
|
|
|
if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
|
2010-02-01 05:38:10 +00:00
|
|
|
return 0;
|
2010-06-02 16:08:41 +00:00
|
|
|
|
|
|
|
/* turn off display hw */
|
|
|
|
list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
|
|
|
|
drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
|
|
|
|
}
|
|
|
|
|
2009-06-05 12:42:42 +00:00
|
|
|
/* unpin the front buffers */
|
|
|
|
list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
|
|
|
|
struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb);
|
2009-11-20 13:29:23 +00:00
|
|
|
struct radeon_bo *robj;
|
2009-06-05 12:42:42 +00:00
|
|
|
|
|
|
|
if (rfb == NULL || rfb->obj == NULL) {
|
|
|
|
continue;
|
|
|
|
}
|
2011-02-18 16:59:17 +00:00
|
|
|
robj = gem_to_radeon_bo(rfb->obj);
|
2010-03-30 05:34:13 +00:00
|
|
|
/* don't unpin kernel fb objects */
|
|
|
|
if (!radeon_fbdev_robj_is_fb(rdev, robj)) {
|
2009-11-20 13:29:23 +00:00
|
|
|
r = radeon_bo_reserve(robj, false);
|
2010-03-30 05:34:13 +00:00
|
|
|
if (r == 0) {
|
2009-11-20 13:29:23 +00:00
|
|
|
radeon_bo_unpin(robj);
|
|
|
|
radeon_bo_unreserve(robj);
|
|
|
|
}
|
2009-06-05 12:42:42 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
/* evict vram memory */
|
2009-11-20 13:29:23 +00:00
|
|
|
radeon_bo_evict_vram(rdev);
|
2009-06-05 12:42:42 +00:00
|
|
|
/* wait for gpu to finish processing current batch */
|
|
|
|
radeon_fence_wait_last(rdev);
|
|
|
|
|
2009-09-15 02:21:01 +00:00
|
|
|
radeon_save_bios_scratch_regs(rdev);
|
|
|
|
|
2010-05-07 19:10:16 +00:00
|
|
|
radeon_pm_suspend(rdev);
|
2009-10-01 16:02:11 +00:00
|
|
|
radeon_suspend(rdev);
|
2009-12-04 21:56:37 +00:00
|
|
|
radeon_hpd_fini(rdev);
|
2009-06-05 12:42:42 +00:00
|
|
|
/* evict remaining vram memory */
|
2009-11-20 13:29:23 +00:00
|
|
|
radeon_bo_evict_vram(rdev);
|
2009-06-05 12:42:42 +00:00
|
|
|
|
2010-05-21 16:48:54 +00:00
|
|
|
radeon_agp_suspend(rdev);
|
|
|
|
|
2009-06-05 12:42:42 +00:00
|
|
|
pci_save_state(dev->pdev);
|
|
|
|
if (state.event == PM_EVENT_SUSPEND) {
|
|
|
|
/* Shut down the device */
|
|
|
|
pci_disable_device(dev->pdev);
|
|
|
|
pci_set_power_state(dev->pdev, PCI_D3hot);
|
|
|
|
}
|
2011-01-25 23:07:35 +00:00
|
|
|
console_lock();
|
2010-03-30 05:34:13 +00:00
|
|
|
radeon_fbdev_set_suspend(rdev, 1);
|
2011-01-25 23:07:35 +00:00
|
|
|
console_unlock();
|
2009-06-05 12:42:42 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int radeon_resume_kms(struct drm_device *dev)
|
|
|
|
{
|
2010-06-11 18:40:56 +00:00
|
|
|
struct drm_connector *connector;
|
2009-06-05 12:42:42 +00:00
|
|
|
struct radeon_device *rdev = dev->dev_private;
|
|
|
|
|
2010-12-06 23:20:40 +00:00
|
|
|
if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
|
2010-02-01 05:38:10 +00:00
|
|
|
return 0;
|
|
|
|
|
2011-01-25 23:07:35 +00:00
|
|
|
console_lock();
|
2009-06-05 12:42:42 +00:00
|
|
|
pci_set_power_state(dev->pdev, PCI_D0);
|
|
|
|
pci_restore_state(dev->pdev);
|
|
|
|
if (pci_enable_device(dev->pdev)) {
|
2011-01-25 23:07:35 +00:00
|
|
|
console_unlock();
|
2009-06-05 12:42:42 +00:00
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
pci_set_master(dev->pdev);
|
2009-11-05 05:39:10 +00:00
|
|
|
/* resume AGP if in use */
|
|
|
|
radeon_agp_resume(rdev);
|
2009-10-01 16:02:11 +00:00
|
|
|
radeon_resume(rdev);
|
2010-05-07 19:10:16 +00:00
|
|
|
radeon_pm_resume(rdev);
|
2009-09-15 02:21:01 +00:00
|
|
|
radeon_restore_bios_scratch_regs(rdev);
|
2010-06-11 18:40:56 +00:00
|
|
|
|
2010-03-30 05:34:13 +00:00
|
|
|
radeon_fbdev_set_suspend(rdev, 0);
|
2011-01-25 23:07:35 +00:00
|
|
|
console_unlock();
|
2009-06-05 12:42:42 +00:00
|
|
|
|
2011-05-22 17:20:36 +00:00
|
|
|
/* init dig PHYs */
|
|
|
|
if (rdev->is_atom_bios)
|
|
|
|
radeon_atom_encoder_init(rdev);
|
2009-12-04 21:56:37 +00:00
|
|
|
/* reset hpd state */
|
|
|
|
radeon_hpd_init(rdev);
|
2009-06-05 12:42:42 +00:00
|
|
|
/* blat the mode back in */
|
|
|
|
drm_helper_resume_force_mode(dev);
|
2010-12-20 16:22:29 +00:00
|
|
|
/* turn on display hw */
|
|
|
|
list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
|
|
|
|
drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
|
|
|
|
}
|
2009-06-05 12:42:42 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-03-09 14:45:12 +00:00
|
|
|
int radeon_gpu_reset(struct radeon_device *rdev)
|
|
|
|
{
|
|
|
|
int r;
|
2011-02-10 04:46:06 +00:00
|
|
|
int resched;
|
2010-03-09 14:45:12 +00:00
|
|
|
|
2011-11-10 17:57:26 +00:00
|
|
|
/* Prevent CS ioctl from interfering */
|
|
|
|
radeon_mutex_lock(&rdev->cs_mutex);
|
|
|
|
|
2010-03-09 14:45:12 +00:00
|
|
|
radeon_save_bios_scratch_regs(rdev);
|
2011-02-10 04:46:06 +00:00
|
|
|
/* block TTM */
|
|
|
|
resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
|
2010-03-09 14:45:12 +00:00
|
|
|
radeon_suspend(rdev);
|
|
|
|
|
|
|
|
r = radeon_asic_reset(rdev);
|
|
|
|
if (!r) {
|
|
|
|
dev_info(rdev->dev, "GPU reset succeed\n");
|
|
|
|
radeon_resume(rdev);
|
|
|
|
radeon_restore_bios_scratch_regs(rdev);
|
|
|
|
drm_helper_resume_force_mode(rdev->ddev);
|
2011-02-10 04:46:06 +00:00
|
|
|
ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
|
2010-03-09 14:45:12 +00:00
|
|
|
}
|
2011-11-10 17:57:26 +00:00
|
|
|
|
|
|
|
radeon_mutex_unlock(&rdev->cs_mutex);
|
|
|
|
|
|
|
|
if (r) {
|
|
|
|
/* bad news, how to tell it to userspace ? */
|
|
|
|
dev_info(rdev->dev, "GPU reset failed\n");
|
|
|
|
}
|
|
|
|
|
2010-03-09 14:45:12 +00:00
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
2009-06-05 12:42:42 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Debugfs
|
|
|
|
*/
|
|
|
|
struct radeon_debugfs {
|
|
|
|
struct drm_info_list *files;
|
|
|
|
unsigned num_files;
|
|
|
|
};
|
2011-09-16 20:45:30 +00:00
|
|
|
static struct radeon_debugfs _radeon_debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
|
2009-06-05 12:42:42 +00:00
|
|
|
static unsigned _radeon_debugfs_count = 0;
|
|
|
|
|
|
|
|
int radeon_debugfs_add_files(struct radeon_device *rdev,
|
|
|
|
struct drm_info_list *files,
|
|
|
|
unsigned nfiles)
|
|
|
|
{
|
|
|
|
unsigned i;
|
|
|
|
|
|
|
|
for (i = 0; i < _radeon_debugfs_count; i++) {
|
|
|
|
if (_radeon_debugfs[i].files == files) {
|
|
|
|
/* Already registered */
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
2011-09-16 20:45:30 +00:00
|
|
|
|
|
|
|
i = _radeon_debugfs_count + 1;
|
|
|
|
if (i > RADEON_DEBUGFS_MAX_COMPONENTS) {
|
|
|
|
DRM_ERROR("Reached maximum number of debugfs components.\n");
|
|
|
|
DRM_ERROR("Report so we increase "
|
|
|
|
"RADEON_DEBUGFS_MAX_COMPONENTS.\n");
|
2009-06-05 12:42:42 +00:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
_radeon_debugfs[_radeon_debugfs_count].files = files;
|
|
|
|
_radeon_debugfs[_radeon_debugfs_count].num_files = nfiles;
|
2011-09-16 20:45:30 +00:00
|
|
|
_radeon_debugfs_count = i;
|
2009-06-05 12:42:42 +00:00
|
|
|
#if defined(CONFIG_DEBUG_FS)
|
|
|
|
drm_debugfs_create_files(files, nfiles,
|
|
|
|
rdev->ddev->control->debugfs_root,
|
|
|
|
rdev->ddev->control);
|
|
|
|
drm_debugfs_create_files(files, nfiles,
|
|
|
|
rdev->ddev->primary->debugfs_root,
|
|
|
|
rdev->ddev->primary);
|
|
|
|
#endif
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
#if defined(CONFIG_DEBUG_FS)
|
|
|
|
int radeon_debugfs_init(struct drm_minor *minor)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void radeon_debugfs_cleanup(struct drm_minor *minor)
|
|
|
|
{
|
|
|
|
unsigned i;
|
|
|
|
|
|
|
|
for (i = 0; i < _radeon_debugfs_count; i++) {
|
|
|
|
drm_debugfs_remove_files(_radeon_debugfs[i].files,
|
|
|
|
_radeon_debugfs[i].num_files, minor);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|