675 lines
23 KiB
PHP
675 lines
23 KiB
PHP
save
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listing off ; kein Listing über diesen File
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;****************************************************************************
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;* *
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;* AS 1.40 - Datei STDDEF60.INC *
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;* *
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;* Sinn : enthält Makrodefinitionen für den PowerPC *
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;* *
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;* letzte Änderungen : 29. 5.1994 *
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;* 26.12.1994 PPC403-Erweiterungen *
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;* 28.12.1994 MPC505-Erweiterungen *
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;* 10. 3.1999 PPC403G[BC]-Erweiterungen *
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;* 28. 3.1999 Korrektur: MMU erst ab PPC403GC *
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;* *
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;****************************************************************************
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ifndef stddef60inc ; verhindert Mehrfacheinbindung
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stddef60inc equ 1
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if (MOMCPU<>1537)&&(MOMCPU<>24576)&&(MOMCPU<>1027)&&(MOMCPU<>1285)&&(MOMCPU<>16443)&&(MOMCPU<>16444)
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fatal "Falscher Prozessortyp eingestellt: nur MPC601, MPC505, PPC403 oder RS6000 erlaubt!"
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endif
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if MOMPASS=1
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message "PowerPC-Makro-Definitionen (C) 1994 Alfred Arnold"
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switch MOMCPU
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case 0x6000
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message "Zielsystem RS6000"
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case 0x601
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message "Zielsystem MPC601"
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case 0x505
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message "Zielsystem MPC505"
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case 0x403,0x403c
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message "Zielsystem PPC403Gx"
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endcase
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endif
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;============================================================================
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; Device-Control-Register
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__defdcr macro NAME,val,{NoExpand}
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NAME equ val
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mt{"NAME"} macro reg
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mtdcr NAME,reg
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endm
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mf{"NAME"} macro reg
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mfdcr reg,NAME
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endm
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endm
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if (MOMCPU=0x403)||(MOMCPU=0x403c)
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__defdcr BEAR,0x90 ; Adresse Busfehler
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__defdcr BESR,0x91 ; Syndrom Busfehler
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__defdcr BR0,0x80 ; Bank-Register 0..7
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__defdcr BR1,0x81
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__defdcr BR2,0x82
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__defdcr BR3,0x83
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__defdcr BR4,0x84
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__defdcr BR5,0x85
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__defdcr BR6,0x86
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__defdcr BR7,0x87
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__defdcr DMACC0,0xc4 ; DMA Kettenzähler (?)
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__defdcr DMACR0,0xc0 ; DMA Steuerregister Kanal 0..3
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__defdcr DMACR1,0xc8
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__defdcr DMACR2,0xd0
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__defdcr DMACR3,0xd8
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__defdcr DMACT0,0xc1 ; DMA Zählregister Kanal 0..3
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__defdcr DMACT1,0xc9
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__defdcr DMACT2,0xd1
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__defdcr DMACT3,0xd9
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__defdcr DMADA0,0xc2 ; DMA Zieladresse Kanal 0..3
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__defdcr DMADA1,0xca
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__defdcr DMADA2,0xd2
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__defdcr DMADA3,0xda
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__defdcr DMASA0,0xc3 ; DMA Quelladresse Kanal 0..3
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__defdcr DMASA1,0xcb
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__defdcr DMASA2,0xd3
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__defdcr DMASA3,0xdb
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__defdcr DMASR,0xe0 ; DMA Statusregister
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__defdcr EXISR,0x40 ; Anzeige externer Interrupts
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__defdcr EXIER,0x42 ; Freigabe externer Interrupts
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__defdcr IOCR,0xa0 ; I/O-Konfiguration
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endif
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;============================================================================
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; Special-Purpose-Register
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__defspr macro NAME,val,{NoExpand}
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NAME equ val
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mt{"NAME"} macro reg
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mtspr NAME,reg
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endm
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mf{"NAME"} macro reg
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mfspr reg,NAME
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endm
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endm
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__defspr XER,0x001 ; Integer Exception Register
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__defspr LR,0x008 ; Rücksprungadresse
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__defspr CTR,0x009 ; Zählregister
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__defspr SRR0,0x01a ; Save/Restore-Register
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__defspr SRR1,0x01b
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__defspr SPRG0,0x110 ; Special Purpose-Register
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__defspr SPRG1,0x111
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__defspr SPRG2,0x112
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__defspr SPRG3,0x113
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switch MOMCPU
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case 0x403,0x403c
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__defspr DAC1,0x3f6 ; Datenadresse Vergleichsregister
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__defspr DAC2,0x3f7
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__defspr DBCR,0x3f2 ; Debug-Steuerregister
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__defspr DBSR,0x3f0 ; Debug-Statusregister
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__defspr DCCR,0x3fa ; Steuerung Daten-Cache
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__defspr DEAR,0x3d5 ; Exception-Adresse Datenzugriff
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__defspr ESR,0x3d4 ; Exception-Syndrom Datenzugriff
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__defspr EVPR,0x3d6 ; Exception-Vektor-Präfix
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__defspr IAC1,0x3f4 ; Codeadresse Vergleichsregister
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__defspr IAC2,0x3f5
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__defspr ICCR,0x3fb ; Steuerung Code-Cache
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__defspr PBL1,0x3fc ; Untergrenzen
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__defspr PBL2,0x3fe
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__defspr PBU1,0x3fd ; Obergrenzen
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__defspr PBU2,0x3ff
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__defspr PIT,0x3db ; Timer
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__defspr PVR,0x11f ; Prozessorversion
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__defspr SRR2,0x3de ; Save/Restore-Register
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__defspr SRR3,0x3df
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__defspr TBHI,0x3dc ; Zeitbasis
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__defspr TBLO,0x3dd
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__defspr TCR,0x3da ; Timer Steuerregister
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__defspr TSR,0x3d8 ; Timer Statusregister
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__defspr SGR,0x3b9 ; ????
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case 0x505
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__defspr TBL,268 ; Zeitbasis
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__defspr TBU,269
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__defspr DSISR,18 ; zeigt Grund von Alignment-Exceptions an
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__defspr DAR,19 ; Fehlerhafte Datenadresse nach Exception
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__defspr DEC,22 ; zählt mit 1 MHz
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__defspr EIE,80 ; Freigabe externer Interrupts
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__defspr EID,81 ; Sperre externer Interrupts
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__defspr NRE,82 ; Non-recoverable Exception
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__defspr TBL_S,284 ; nochmal Zeitbasis ?!
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__defspr TBU_S,285
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__defspr PVR,287 ; Prozessorversion
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__defspr ICCST,560 ; Steuerung & Status Instruktionscache
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__defspr ICADR,561 ; Instruktionscache Adreßregister
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__defspr ICDAT,562 ; Instruktionscache Datenregister
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__defspr FPECR,1022 ; Gleitkommaexception
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__defspr CMPA,144 ; Vergleicherwert A..D
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__defspr CMPB,145
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__defspr CMPC,146
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__defspr CMPD,147
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__defspr ECR,148 ; Grund der Debug-Exception
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__defspr DER,149 ; Freigabe Debug-Features
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__defspr COUNTA,150 ; Breakpoint Zähler
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__defspr COUNTB,151
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__defspr CMPE,152 ; Vergleicherwert E..G
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__defspr CMPF,153
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__defspr CMPG,154
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__defspr CMPH,155
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__defspr LCTRL1,156 ; Debug-Steuerung Vergleicher L-Bus
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__defspr LCTRL2,157
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__defspr ICTRL,158 ; Debug-Steuerung I-Bus
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__defspr BAR,159 ; Breakpoint-Adresse
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__defspr DPDR,630 ; Development-Port Daten
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__defspr DPIR,631 ; " " Instruktionen
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case 0x601
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__defspr RTCU,0x004 ; Zähler
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__defspr RTCL,0x005
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__defspr DEC,0x006
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__defspr DSISR,0x012
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__defspr DAR,0x013
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__defspr DEC2,0x016
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__defspr SDR1,0x019
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__defspr EAR,0x11a
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__defspr BAT0U,0x210
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__defspr BAT0L,0x211
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__defspr BAT1U,0x212
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__defspr BAT1L,0x213
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__defspr BAT2U,0x214
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__defspr BAT2L,0x215
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__defspr BAT3U,0x216
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__defspr BAT3L,0x217
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__defspr HID0,0x3f0
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__defspr HID1,0x3f1
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__defspr HID2,0x3f2
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__defspr HID5,0x3f5
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__defspr HID15,0x3ff
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case 0x6000
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__defspr MQ,0x000 ; obere Hälfte Divident/Produkt
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endcase
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if MOMCPU=0x403c
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__defspr pid, 0x3b1
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endif
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;============================================================================
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; serieller Port PPC403:
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if (MOMCPU=0x403)||(MOMCPU=0x403c)
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spls equ 0x40000000 ; Leitungsstatus
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sphs equ 0x40000002 ; Status Handshake-Leitungen
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brdh equ 0x40000004 ; Baudratenteiler
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brdl equ 0x40000005
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spctl equ 0x40000006 ; Steuerregister
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sprc equ 0x40000007 ; Kommandoregister Empfänger
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sptc equ 0x40000008 ; Kommandoregister Sender
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sprb equ 0x40000009 ; Sende/Empfangspuffer
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sptb equ sprb
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endif
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;============================================================================
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; SIU MPC505:
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; erinnert irgendwie an die vom 6833x...
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if MOMCPU=0x505
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siumcr equ 0x8007fc00 ; Basissteuerregister
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siutest1 equ 0x8007fc04
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memmap equ 0x8007fc20 ; Speicherlayout
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specaddr equ 0x8007fc24 ; erlauben Sperren spekulativer
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specmask equ 0x8007fc28 ; Ladevorgänge
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termstat equ 0x8007fc2c
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picsr equ 0x8007fc40 ; Steuerung periodische Interrupts
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pit equ 0x8007fc44 ; Zählwert periodischer Interrupt-Timer
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bmcr equ 0x8007fc48 ; Steuerung Bus-Monitor
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rsr equ 0x8007fc4c ; Reset-Status
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sccr equ 0x8007fc50 ; Steuerung Systemtakt
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sccsr equ 0x8007fc54 ; Status Systemtakt
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portbase equ 0x8007fc60
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ddrm equ portbase+0x00 ; Datenrichtungsregister Port M
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pmpar equ portbase+0x04 ; Pinzuordnung Port M
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portm equ portbase+0x08 ; Datenregister Port M
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papar equ portbase+0x24 ; Pinzuordnung Port A+B
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pbpar equ papar
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porta equ portbase+0x28 ; Datenregister Port A+B
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portb equ porta
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ddri equ portbase+0x38 ; Datenrichtungsregister Port I..L
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ddrj equ ddri
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ddrk equ ddri
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ddrl equ ddri
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pipar equ portbase+0x38 ; Pinzuordnung Port I..L
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pjpar equ pipar
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pkpar equ pipar
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plpar equ pipar
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porti equ portbase+0x40 ; Datenregister Port I..L
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portj equ porti
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portk equ porti
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portl equ porti
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csbase equ 0x8007fd00
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csbtbar equ csbase+0xf8 ; Basisadresse Boot-EPROM
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csbtsbbar equ csbase+0xf0
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csbar1 equ csbase+0xe0 ; Basisadressen /CS1../CS5
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csbar2 equ csbase+0xd8
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csbar3 equ csbase+0xd0
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csbar4 equ csbase+0xc8
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csbar5 equ csbase+0xc0
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csbtor equ csbase+0xfc ; Optionen Boot-EPROM
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csbtsbor equ csbase+0xf4
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csor0 equ csbase+0xec ; Optionen /CS1../CS11
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csor1 equ csbase+0xe4
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csor2 equ csbase+0xdc
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csor3 equ csbase+0xd4
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csor4 equ csbase+0xcc
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csor5 equ csbase+0xc4
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csor6 equ csbase+0xbc
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csor7 equ csbase+0xb4
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csor8 equ csbase+0xac
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csor9 equ csbase+0xa4
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csor10 equ csbase+0x9c
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csor11 equ csbase+0x94
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endif
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;----------------------------------------------------------------------------
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; Peripheral Control Unit MPC505:
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if MOMCPU=0x505
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pcubase equ 0x8007ef80
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pcumcr equ pcubase+0x00 ; Basiskonfiguration
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tstmsra equ pcubase+0x10
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tstmsrb equ tstmsra
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tstcntrab equ pcubase+0x14
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tstreps equ tstcntrab
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tstcreg1 equ pcubase+0x18
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tstcreg2 equ tstcreg1
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tstdreg equ pcubase+0x1c
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irqpend equ pcubase+0x20 ; auszuführende Interrupts
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irqand equ pcubase+0x24 ; freigegebene&auszuführende Interrupts
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irqenable equ pcubase+0x28 ; freigegebene Interrupts
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pitqil equ pcubase+0x2c ; Interruptebene PortQ/PIT
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swsr equ pcubase+0x40 ; Reload Watchdog auslösen
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swcr equ pcubase+0x44 ; Steuerung Watchdog
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swtc equ swcr
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swr equ pcubase+0x48
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pqedgdat equ pcubase+0x50 ; Flankenauswahl PortQ
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pqpar equ pcubase+0x54 ; Pinzuordnung PortQ
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endif
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;----------------------------------------------------------------------------
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; SRAM-Modul MPC505:
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if MOMCPU=0x505
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srammcr equ 0x8007f00 ; Basiskonfiguration SRAM
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endif
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;============================================================================
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; SUBI geht sowohl mit 2 als auch 3 Argumenten
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subi macro dest,src,VAL
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if "VAL"=""
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addi dest,dest,-src
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elseif
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addi dest,src,-VAL
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endif
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endm
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;----------------------------------------------------------------------------
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; Vergleiche
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cmpw macro cr,REG1,REG2
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if "REG2"=""
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cmp 0,0,cr,REG1
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elseif
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cmp cr,0,REG1,REG2
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endif
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endm
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cmpwi macro cr,REG1,IMM
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if "IMM"=""
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cmpi 0,0,cr,IMM
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elseif
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cmpi cr,0,REG1,imm
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endif
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endm
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cmplw macro cr,REG1,REG2
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if "REG2"=""
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cmpl 0,0,cr,REG1
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elseif
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cmpl cr,0,REG1,REG2
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endif
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endm
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cmplwi macro cr,REG1,IMM
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if "IMM"=""
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cmpli 0,0,cr,IMM
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elseif
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cmpli cr,0,REG1,IMM
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endif
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endm
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;----------------------------------------------------------------------------
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; erweiterte Befehle Bedingungsregister
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crset macro bx
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creqv bx,bx,bx
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endm
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crnot macro bx,by
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crnor bx,by,by
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endm
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crmove macro bx,by
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cror bx,by,by
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endm
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;----------------------------------------------------------------------------
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; erweiterte Befehle Logik
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not macro dest,SRC
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if "SRC"=""
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nor dest,dest
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elseif
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nor dest,SRC,SRC
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endif
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endm
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not. macro dest,SRC
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if "SRC"=""
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nor. dest,dest
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elseif
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nor. dest,SRC,SRC
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endif
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endm
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mr macro dest,src
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or dest,src,src
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endm
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mr. macro dest,src
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or. dest,src,src
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endm
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nop macro
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ori 0,0,0
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endm
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;----------------------------------------------------------------------------
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; vereinfachte Einschiebebefehle
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inslwi macro ra,rs,n,b
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rlwimi ra,rs,32-b,b,b+n-1
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endm
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inslwi. macro ra,rs,n,b
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rlwimi. ra,rs,32-b,b,b+n-1
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endm
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insrwi macro ra,rs,n,b
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rlwimi ra,rs,32-b-n,b,b+n-1
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endm
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insrwi. macro ra,rs,n,b
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rlwimi. ra,rs,32-b-n,b,b+n-1
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endm
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__defins1 macro NAME,par1,par2,par3,{NoExpand}
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{"NAME"} macro ra,rs,n
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rlwinm ra,rs,par1,par2,par3
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endm
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{"NAME"}. macro ra,rs,n
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rlwinm. ra,rs,par1,par2,par3
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endm
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endm
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__defins2 macro NAME,par1,par2,par3,{NoExpand}
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{"NAME"} macro ra,rs,b,n
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rlwinm ra,rs,par1,par2,par3
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endm
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{"NAME"}. macro ra,rs,b,n
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rlwinm. ra,rs,par1,par2,par3
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endm
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endm
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__defins1 clrlwi,0,n,31
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__defins2 clrlslwi,n,b-n,31-n
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__defins1 clrrwi,0,0,31-n
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__defins2 extlwi,b,0,n-1
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__defins2 extrwi,b+n,32-n,31
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__defins1 rotlwi,n,0,31
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__defins1 rotrwi,32-n,0,31
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__defins1 slwi,n,0,31-n
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__defins1 srwi,32-n,n,31
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rotlw macro ra,rs,rb
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rlwnm ra,rs,rb,0,31
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endm
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rotlw. macro ra,rs,rb
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rlwnm. ra,rs,rb,0,31
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endm
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;----------------------------------------------------------------------------
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; vereinfachte Sprünge
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__defjmp1 macro NAME,m1,m2,{NoExpand}
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{"NAME"} macro adr
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bc m1,m2,adr
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endm
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{"NAME"}a macro adr
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bca m1,m2,adr
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endm
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{"NAME"}l macro adr
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bcl m1,m2,adr
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endm
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{"NAME"}la macro adr
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bcla m1,m2,adr
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endm
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endm
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__defjmp1 bdnz,16,0
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__defjmp1 bdz,18,0
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__defjmp2 macro NAME,m1,{NoExpand}
|
|
{"NAME"} macro cr,adr
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bc m1,cr,adr
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endm
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{"NAME"}a macro cr,adr
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bca m1,cr,adr
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endm
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{"NAME"}l macro cr,adr
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bcl m1,cr,adr
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endm
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{"NAME"}la macro cr,adr
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bcla m1,cr,adr
|
|
endm
|
|
endm
|
|
|
|
__defjmp2 bdnzf,0
|
|
__defjmp2 bdnzt,8
|
|
__defjmp2 bdzf,2
|
|
__defjmp2 bdzt,10
|
|
__defjmp2 bf,4
|
|
__defjmp2 bt,12
|
|
|
|
__defjmp3 macro NAME,mask,ofs,{NoExpand}
|
|
{"NAME"} macro cr,ADR
|
|
if "ADR"=""
|
|
bc mask,ofs,cr
|
|
elseif
|
|
bc mask,cr*4+ofs,adr
|
|
endif
|
|
endm
|
|
{"NAME"}a macro cr,ADR
|
|
if "ADR"=""
|
|
bca mask,ofs,cr
|
|
elseif
|
|
bca mask,cr*4+ofs,adr
|
|
endif
|
|
endm
|
|
{"NAME"}l macro cr,ADR
|
|
if "ADR"=""
|
|
bcl mask,ofs,cr
|
|
elseif
|
|
bcl mask,cr*4+ofs,adr
|
|
endif
|
|
endm
|
|
{"NAME"}la macro cr,ADR
|
|
if "ADR"=""
|
|
bcla mask,ofs,cr
|
|
elseif
|
|
bcla mask,cr*4+ofs,adr
|
|
endif
|
|
endm
|
|
{"NAME"}ctr macro CR
|
|
if "CR"=""
|
|
bcctr mask,ofs
|
|
elseif
|
|
bc mask,CR*4+ofs
|
|
endif
|
|
endm
|
|
{"NAME"}ctrl macro CR
|
|
if "CR"=""
|
|
bcl mask,ofs
|
|
elseif
|
|
bcl mask,CR*4+ofs
|
|
endif
|
|
endm
|
|
{"NAME"}lr macro CR
|
|
if "CR"=""
|
|
bclr mask,ofs
|
|
elseif
|
|
bclr mask,4*CR+ofs
|
|
endif
|
|
endm
|
|
{"NAME"}lrl macro CR
|
|
if "CR"=""
|
|
bclrl mask,ofs
|
|
elseif
|
|
bclrl mask,4*CR+ofs
|
|
endif
|
|
endm
|
|
endm
|
|
|
|
__defjmp3 beq,12,2
|
|
__defjmp3 bge,4,0
|
|
__defjmp3 bgt,12,1
|
|
__defjmp3 ble,4,1
|
|
__defjmp3 blt,12,0
|
|
__defjmp3 bne,4,2
|
|
__defjmp3 bng,4,1
|
|
__defjmp3 bnl,4,0
|
|
__defjmp3 bns,4,3
|
|
__defjmp3 bnu,4,3
|
|
__defjmp3 bso,12,3
|
|
__defjmp3 bun,12,3
|
|
|
|
bctr macro
|
|
bcctr 20,0
|
|
endm
|
|
bctrl macro
|
|
bcctrl 20,0
|
|
endm
|
|
|
|
__defjmp4 macro NAME,mask,{NoExpand}
|
|
{"NAME"} macro cr
|
|
bcctr mask,cr
|
|
endm
|
|
{"NAME"}l macro cr
|
|
bcctrl mask,cr
|
|
endm
|
|
endm
|
|
|
|
__defjmp4 bfctr,4
|
|
__defjmp4 btctr,12
|
|
|
|
__defjmp6 macro NAME,mask,bit,{NoExpand}
|
|
{"NAME"} macro
|
|
bclr mask,bit
|
|
endm
|
|
{"NAME"}l macro
|
|
bclrl mask,bit
|
|
endm
|
|
endm
|
|
|
|
__defjmp6 blr,20,0
|
|
__defjmp6 bdnzlr,16,0
|
|
__defjmp6 bdzlr,18,0
|
|
|
|
__defjmp7 macro NAME,mask,{NoExpand}
|
|
{"NAME"} macro cr
|
|
bclr mask,cr
|
|
endm
|
|
{"NAME"}l macro cr
|
|
bclrl mask,cr
|
|
endm
|
|
endm
|
|
|
|
__defjmp7 bdnzflr,0
|
|
__defjmp7 bdnztlr,8
|
|
__defjmp7 bdzflr,2
|
|
__defjmp7 bdztlr,10
|
|
__defjmp7 bflr,4
|
|
__defjmp7 btlr,12
|
|
|
|
;-------------------------------------------------------------------------
|
|
; Traps
|
|
|
|
trap macro ra,rb
|
|
tw 31,ra,rb
|
|
endm
|
|
|
|
__deftrap macro NAME,mask,{NoExpand}
|
|
{"NAME"} macro ra,rb
|
|
tw mask,ra,rb
|
|
endm
|
|
{"NAME"}i macro ra,im
|
|
twi mask,ra,im
|
|
endm
|
|
endm
|
|
|
|
__deftrap tweq,4
|
|
__deftrap twge,12
|
|
__deftrap twgt,8
|
|
__deftrap twle,20
|
|
__deftrap twlge,5
|
|
__deftrap twlgt,1
|
|
__deftrap twlle,6
|
|
__deftrap twllt,2
|
|
__deftrap twlng,6
|
|
__deftrap twlnl,5
|
|
__deftrap twlt,16
|
|
__deftrap twne,24
|
|
__deftrap twng,20
|
|
__deftrap twnl,12
|
|
|
|
;-------------------------------------------------------------------------
|
|
; MMU-Makros PPC403G[BC]
|
|
|
|
if (MOMCPU=0x403c)||(MOMCPU=0x403c)
|
|
|
|
tlbrehi macro rt,ra
|
|
tlbre rt,ra,0
|
|
endm
|
|
|
|
tlbrelo macro rt,ra
|
|
tlbre rt,ra,1
|
|
endm
|
|
|
|
tlbwehi macro rt,ra
|
|
tlbwe rt,ra,0
|
|
endm
|
|
|
|
tlbwelo macro rt,ra
|
|
tlbwe rt,ra,1
|
|
endm
|
|
|
|
endif
|
|
|
|
;=========================================================================
|
|
|
|
endif
|
|
|
|
restore ; Listing wieder erlauben
|
|
|