121 lines
4.8 KiB
PHP
121 lines
4.8 KiB
PHP
save
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; listing off ; kein Listing über diesen File
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;****************************************************************************
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;* *
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;* AS 1.41 - Datei REG7000.INC *
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;* *
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;* Sinn : enthält SFR- und Bitdefinitionen für die TMS70Cxx-Prozessoren *
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;* *
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;* letzte Änderungen : 15. 2.1997 *
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;* *
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;****************************************************************************
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ifndef reg7000inc ; verhindert Mehrfacheinbindung
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reg7000inc equ 1
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switch MOMCPUNAME
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case "TMS70C40"
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IROM equ 0f000h
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__group equ 1
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case "TMS70C20"
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IROM equ 0f800h
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__group equ 1
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case "TMS70C00"
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IROM equ 10000h
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__group equ 1
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case "TMS70CT40"
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IROM equ 0f000h
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__group equ 2
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case "TMS70CT20"
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IROM equ 0f800h
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__group equ 2
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case "TMS70C82"
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IROM equ 0e000h
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__group equ 3
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case "TMS70C42"
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IROM equ 0f000h
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__group equ 3
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case "TMS70C02"
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IROM equ 0f800h
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__group equ 3
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case "TMS70C48"
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IROM equ 0f000h
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__group equ 4
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case "TMS70C08"
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IROM equ 10000h
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__group equ 4
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elsecase
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fatal "Fehler: nur TMS70Cxx-Prozessoren erlaubt!"
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endcase
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if MOMPASS=1
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message "TMS7000-Register-Definitionen (C) 1997 Alfred Arnold"
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endif
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;----------------------------------------------------------------------------
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; Speicherbereiche
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IRAM equ 0
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IROMEND equ 0ffffh
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if __group<=2
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IRAMEND equ 127
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elseif
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IRAMEND equ 255
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endif
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;----------------------------------------------------------------------------
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; Peripherie
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IOCNT0 equ p0 ; I/O Control Register 0
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APORT equ p4 ; Port A Data
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BPORT equ p6 ; Port B Data
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CPORT equ p8 ; Port C Data
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CDDR equ p9 ; Port C Data Direction Register
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DPORT equ p10 ; Port D Data
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DDDR equ p11 ; Port D Data Direction Register
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if __group<=2
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T1DATA equ p2 ; Timer 1 Data
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T1CTL equ p3 ; Timer 1 Control
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endif
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if __group>=3
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IOCNT2 equ p1 ; I/O Control Register 2
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IOCNT1 equ p2 ; I/O Control Register 1
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ADDR equ p5 ; Port A Data Direction Register
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T1MSDATA equ p12 ; Timer 1 MSB Dec. Reload / Readout Latch
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T1LSDATA equ p13 ; Timer 1 LSB Reload / Dec. Value
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T1CTL1 equ p14 ; Timer 1 Control Register 1 / MSB Readout Latch
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T1CTL0 equ p15 ; Timer 1 Control Register 0 / LSB Capture Latch
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T2MSDATA equ p16 ; Timer 2 MSB Dec. Reload / Readout Latch
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T2LSDATA equ p17 ; Timer 2 LSB Reload / Dec. Value
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T2CTL1 equ p18 ; Timer 2 Control Register 1 / MSB Readout Latch
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T2CTL0 equ p19 ; Timer 2 Control Register 0 / LSB Capture Latch
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SMODE equ p20 ; Serial Port Mode Control Register
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SCTL0 equ p21 ; Serial Port Control Register 0
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SSTAT equ p22 ; Serial Port Status Register
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T3DATA equ p23 ; Timer 3 Reload Reg. / Decr. Value
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SCTL1 equ p24 ; Serial Port Control Register 1
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RXBUF equ p25 ; Receiver Buffer
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TXBUF equ p26 ; Transmitter Buffer
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endif
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if __group=4
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EPORT equ p28 ; Port E Data
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EDDR equ p29 ; Port E Data Direction Register
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FPORT equ p30 ; Port F Data
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FDDR equ p31 ; Port F Data Direction Register
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GPORT equ p32 ; Port G Data
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GDDR equ p33 ; Port G Data Direction Register
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endif
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;----------------------------------------------------------------------------
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endif
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restore ; wieder erlauben
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