701 lines
37 KiB
PHP
701 lines
37 KiB
PHP
save
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listing off ; kein Listing über diesen File
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macexp off ; spart noch ein bißchen Zeit
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;****************************************************************************
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;* *
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;* AS 1.40 - Datei REG96.INC *
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;* *
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;* Sinn : enthält Registeradreßdefinitionen für 68332 und 68340 *
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;* *
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;* letzte Änderungen : 18.11.1994 *
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;* *
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;****************************************************************************
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ifndef reg68332inc ; verhindert Mehrfacheinbindung
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reg6833xinc equ 1
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if (MOMCPUNAME<>"68332")&&(MOMCPUNAME<>"68340")&&(MOMCPUNAME<>"68360")
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fatal "Falscher Prozessortyp eingestellt: nur 68332 oder 68340 erlaubt!"
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endif
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if MOMPASS=1
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message "CPU32-Register-Definitionen (C) 1994 Alfred Arnold"
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message "binde \{MOMCPU}-Register ein"
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endif
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;-----------------------------------------------------------------------------
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; Basis ist entweder $fffa00 oder $7fa000, das muß man vorher setzen
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; (oder mit dem Default leben :-)
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; beim 68340 kann man ganz frei wählen
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; Da der 68332 A31..A24 nicht herausführt, könnte man evtl. auch die Register
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; ab $fffffa00 erreichen und kurze Adressen verwenden. Das müßte man mal
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; ausprobieren...alternativ kann man man aber auch die Basis auf 0 setzen,
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; bevor man diese Datei einbindet und dann die Symbole registerrelativ
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; verwenden.
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ifndef SIMBase
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if MOMCPU=$68332
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SIMBase equ $fffa00
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elseif
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SIMBase equ $000000
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endif
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endif
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;=============================================================================
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; Da sich 68360, 68340 und 68332 sehr deutlich im Registermodell unterscheiden,
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; habe ich mir keine Mühe gemacht, Register für Register auseinanderzufieseln,
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; was gemeinsam ist und was nicht
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switch MOMCPUNAME
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;-----------------------------------------------------------------------------
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case "68360"
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;-----------------------------------------------------------------------------
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MBAR equ $0003ff00 ; [L] Startadresse Peripherie (CPU-Space!)
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MBARE equ $0003ff04 ; [L] Sperrung/Freigabe MBAR
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RegBase equ SIMBase+$1000 ; Startadresse Rgister
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MCR equ RegBase+$0000 ; [L] Modulkonfiguration SIM
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AVR equ RegBase+$0008 ; [B] Freigabe Autovektor-Interrupts
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RSR equ RegBase+$0009 ; [B] Reset-Status
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CLK0CR equ RegBase+$000c ; [B] Steuerung Taktausgang 2 & 1
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PLLCR equ RegBase+$0010 ; [W] PLL-Steuerung
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CDVCR equ RegBase+$0014 ; [W] Steuerung "langsamer" Takt
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PEPAR equ RegBase+$0016 ; [W] Zuordnung der I/O-Pins Port E
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SYPCR equ RegBase+$0022 ; [B] Systemmonitore, Bustimimg
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SWIV equ RegBase+$0023 ; [B] Interruptvektor Watchdog
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PICR equ RegBase+$0026 ; [W] Interruptebene+ -vektor period. Interrupt
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PITR equ RegBase+$002a ; [W] Zählwert & Vorteiler period. Interrupt
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SWSR equ RegBase+$002f ; [B] Watchdog rücksetzen
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BKAR equ RegBase+$0030 ; [L] Breakpoint-Adresse
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BKCR equ RegBase+$0034 ; [L] Breakpoint-Steuerung
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GMR equ RegBase+$0040 ; [L] globale Steuerung Memory-Controller
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MSTAT equ RegBase+$0044 ; [W] Status Memory-Controller
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BR0 equ RegBase+$0050 ; [L] SRAM/DRAM-Basis CS0
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OR0 equ RegBase+$0054 ; [L] Optionen DRAM/SRAM CS0
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BR1 equ RegBase+$0060 ; [L] SRAM/DRAM-Basis CS1
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OR1 equ RegBase+$0064 ; [L] Optionen DRAM/SRAM CS1
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BR2 equ RegBase+$0070 ; [L] SRAM/DRAM-Basis CS2
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OR2 equ RegBase+$0074 ; [L] Optionen DRAM/SRAM CS2
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BR3 equ RegBase+$0080 ; [L] SRAM/DRAM-Basis CS3
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OR3 equ RegBase+$0084 ; [L] Optionen DRAM/SRAM CS3
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BR4 equ RegBase+$0090 ; [L] SRAM/DRAM-Basis CS4
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OR4 equ RegBase+$0094 ; [L] Optionen DRAM/SRAM CS4
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BR5 equ RegBase+$00a0 ; [L] SRAM/DRAM-Basis CS5
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OR5 equ RegBase+$00a4 ; [L] Optionen DRAM/SRAM CS5
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BR6 equ RegBase+$00b0 ; [L] SRAM/DRAM-Basis CS6
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OR6 equ RegBase+$00b4 ; [L] Optionen DRAM/SRAM CS6
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BR7 equ RegBase+$00c0 ; [L] SRAM/DRAM-Basis CS7
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OR7 equ RegBase+$00c4 ; [L] Optionen DRAM/SRAM CS7
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;-----------------------------------------------------------------------------
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; Communications Controller:
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RAMBase equ SIMBase ; [ ] RAM-Basisadresse
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;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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; IDMA:
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IDMA1Base equ RAMBase+$0e70
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IDMA2Base equ RAMBase+$0f70
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ICCR equ RegBase+$0500 ; [W] Konfiguration IDMA-Kanäle
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CMR1 equ RegBase+$0504 ; [W] Modus IDMA1
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CMR2 equ RegBase+$0526 ; [W] Modus IDMA2
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__defidma macro NAME,Adr,IDMABase
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SAPR{NAME} equ Adr ; [L] Quelladresse bei Speicherkopieraktionen
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DAPR{NAME} equ Adr+4 ; [L] Zieladresse " "
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BCR{NAME} equ Adr+8 ; [L] Zählregister IDMA
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FCR{NAME} equ Adr+12 ; [B] Funktionscodes
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CMAR{NAME} equ Adr+14 ; [B] Kanalmaske
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CSR{NAME} equ Adr+16 ; [B] Kanalstatus IDMA
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IDMA{NAME}_IBASE equ IDMABase+0 ; [W] Basisadresse Deskriptor
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IDMA{NAME}_IBPTR equ IDMABase+0 ; [W] Pointer Deskriptor
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IDMA{NAME}_ISTATE equ IDMABase+0 ; [L] int. Status
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IDMA{NAME}_ITEMP equ IDMABase+0 ; [L] temp. Speicher
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endm
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__defidma "1",RegBase+$508
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__defidma "2",RegBase+$528
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;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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; SDMA:
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SDSR equ RegBase+$051c ; [B] Status SDMA
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SDCR equ RegBase+$051e ; [W] Konfiguration SDMA-Kanäle
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SDAR equ RegBase+$0520 ; [L] SDMA-Adreßregister
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;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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; CPIC:
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CICR equ RegBase+$0540 ; [L] Interrupt-Konfiguration
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CIPR equ RegBase+$0544 ; [L] Interrupt-Anzeigen
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CIMR equ RegBase+$0548 ; [L] Interrupt-Masken
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CISR equ RegBase+$054c ; [L] Anzeige, ob Interrupts in Bearbeitung
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;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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; PIO:
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PADIR equ RegBase+$0550 ; [W] Datenrichtungsregister Port A
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PAPAR equ RegBase+$0552 ; [W] Zuordnung Port A
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PAODR equ RegBase+$0554 ; [W] Steuerbits Port A als open drain
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PADAT equ RegBase+$0556 ; [W] Datenregister Port A
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PCDIR equ RegBase+$0560 ; [W] Datenrichtungsregister Port C
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PCPAR equ RegBase+$0562 ; [W] Zuordnung Port C
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PCSO equ RegBase+$0564 ; [W] Special Options Port C
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PCDAT equ RegBase+$0566 ; [W] Datenregister Port C
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PCINT equ RegBase+$0568 ; [W] Interruptsteuerung Port C
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;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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; TIMER:
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TimerBase equ RAMBase+$0db0
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TGCR equ RegBase+$0560 ; [W] globale Konfiguration Timer
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TMR1 equ RegBase+$0590 ; [W] Modus Timer 1
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TRR1 equ RegBase+$0594 ; [W] Referenzwert Timer 1
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TCR1 equ RegBase+$0598 ; [W] Fangwert Timer 1
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TCN1 equ RegBase+$059c ; [W] Zählwert Timer 1
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TER1 equ RegBase+$05b0 ; [W] Ereignismeldung Timer 1
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TMR2 equ RegBase+$0592
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TRR2 equ RegBase+$0596
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TCR2 equ RegBase+$059a
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TCN2 equ RegBase+$059e
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TER2 equ RegBase+$05b2
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TMR3 equ RegBase+$05a0
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TRR3 equ RegBase+$05a4
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TCR3 equ RegBase+$05a8
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TCN3 equ RegBase+$05ac
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TER3 equ RegBase+$05b4
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TMR4 equ RegBase+$05a2
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TRR4 equ RegBase+$05a6
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TCR4 equ RegBase+$05aa
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TCN4 equ RegBase+$05ae
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TER4 equ RegBase+$05b6
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TIMER_TM_BASE equ TimerBase+$00 ; [W] Basisadresse Tabelle
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TIMER_TM_ptr equ TimerBase+$02 ; [W] Zeiger Tabelle
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TIMER_R_TMR equ TimerBase+$04 ; [W] Modus
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TIMER_R_TMV equ TimerBase+$06 ; [W] Valid-Register
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TIMER_TM_cmd equ TimerBase+$08 ; [L] Kommandoregister
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TIMER_TM_cnt equ TimerBase+$0c ; [L] interner Zähler
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;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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; CP:
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MiscBase equ RAMBase+$0cb0
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CR equ RegBase+$05c0 ; [W] Kommandoregister
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RCCR equ RegBase+$05c4 ; [W] Konfiguration RISC-Controller
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RTER equ RegBase+$05d6 ; [W] Timer-Events
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RTMR equ RegBase+$05da ; [W] Timer-Maske
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CP_REV_num equ MiscBase ; [W] Revisionsnummer Mikrocode
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;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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; BRG:
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BRGC1 equ RegBase+$05f0 ; [L] Konfiguration Baudratengenerator 1
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BRGC2 equ RegBase+$05f4
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BRGC3 equ RegBase+$05f8
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BRGC4 equ RegBase+$05fc
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;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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; SCC:
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SCC1Base equ RAMBase+$0c00
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SCC2Base equ RAMBase+$0d00
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SCC3Base equ RAMBase+$0e00
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SCC4Base equ RAMBase+$0f00
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__defscc macro NAME,Adr,SCCBase
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GSMR_L{NAME} equ Adr+0 ; [Q] Modus
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GSMR_H{NAME} equ Adr+4
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PSMR{NAME} equ Adr+8 ; [W] protokollspez. Modus
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TODR{NAME} equ Adr+12 ; [W] Sendestart erzwingen
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DSR{NAME} equ Adr+14 ; [W] Synchronisationsmuster SCCx
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SCCE{NAME} equ Adr+16 ; [W] Ereignisregister UART
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SCCM{NAME} equ Adr+20 ; [W] UART Ereignismaske
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SCCS{NAME} equ Adr+23 ; [B] UART Status
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SCC{NAME}_RBASE equ SCCBase+$00 ; [W] Startadresse Empfangspuffer
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SCC{NAME}_TBASE equ SCCBase+$02 ; [W] Startadresse Sendepuffer
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SCC{NAME}_RFCR equ SCCBase+$04 ; [B] Adreßraum Empfangen
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SCC{NAME}_TFCR equ SCCBase+$05 ; [B] Adreßraum Senden
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SCC{NAME}_MRBLR equ SCCBase+$06 ; [W] Länge Empfangspuffer
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SCC{NAME}_RSTATE equ SCCBase+$08 ; [L] Status Empfänger
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SCC{NAME}_RBPTR equ SCCBase+$10 ; [W] Adreßzeiger Empfangen
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SCC{NAME}_TSTATE equ SCCBase+$18 ; [L] Status Sender
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SCC{NAME}_TBPTR equ SCCBase+$20 ; [W] Adreßzeiger Senden
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SCC{NAME}_RCRC equ SCCBase+$28 ; [L] Empfangs-CRC
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SCC{NAME}_TCRC equ SCCBase+$2c ; [L] Sende-CRC
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SCC{NAME}_MAX_IDL equ SCCBase+$38 ; [W] --UART-- Maximalzahl Idle-Zeichen
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SCC{NAME}_IDLC equ SCCBase+$3a ; [W] temp. Idle-Zähler
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SCC{NAME}_BRKCR equ SCCBase+$3c ; [W] Anzahl Sende-Breaks
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SCC{NAME}_PAREC equ SCCBase+$3e ; [W] Paritätsfehlerzähler
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SCC{NAME}_FRMEC equ SCCBase+$40 ; [W] Rahmungs-Fehlerzähler
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SCC{NAME}_NOSEC equ SCCBase+$42 ; [W] Rauschzähler
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SCC{NAME}_BRKEC equ SCCBase+$44 ; [W] Break-Bedingung
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SCC{NAME}_BRKLN equ SCCBase+$46 ; [W] Länge des letzten Breaks
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SCC{NAME}_UADDR1 equ SCCBase+$48 ; [W] Slave-Adressen
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SCC{NAME}_UADDR2 equ SCCBase+$4a ; [W]
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SCC{NAME}_RTEMP equ SCCBase+$4c ; [W] temp. Speicher
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SCC{NAME}_TOSEQ equ SCCBase+$4e ; [W] out-of-sequence Zeichen
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SCC{NAME}_CHARACTER1 equ SCCBase+$50 ; [W] Zeichen, die Interrupts erzeugen
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SCC{NAME}_CHARACTER2 equ SCCBase+$52 ; [W]
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SCC{NAME}_CHARACTER3 equ SCCBase+$54 ; [W]
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SCC{NAME}_CHARACTER4 equ SCCBase+$56 ; [W]
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SCC{NAME}_CHARACTER5 equ SCCBase+$58 ; [W]
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SCC{NAME}_CHARACTER6 equ SCCBase+$5a ; [W]
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SCC{NAME}_CHARACTER7 equ SCCBase+$5c ; [W]
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SCC{NAME}_CHARACTER8 equ SCCBase+$5e ; [W]
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SCC{NAME}_RCCM equ SCCBase+$60 ; [W] Maske Empfangszeichen
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SCC{NAME}_RCCR equ SCCBase+$62 ; [W] Empfangszeichen
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SCC{NAME}_RLBC equ SCCBase+$64 ; [W] letztes Break-Zeichen
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SCC{NAME}_C_MASK equ SCCBase+$34 ; [L] --HDLC-- CRC-Polynom
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SCC{NAME}_C_PRES equ SCCBase+$38 ; [L] CRC-Startwert
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SCC{NAME}_DISFC equ SCCBase+$3c ; [W] Zähler für verworfene Rahmen
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SCC{NAME}_CRCEC equ SCCBase+$3e ; [W] Zähler für CRC-Fehler
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SCC{NAME}_ABTSC equ SCCBase+$40 ; [W] Zähler für Abbrüche
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SCC{NAME}_NMARC equ SCCBase+$42 ; [W] Zähler für unpassende Adressen
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SCC{NAME}_RETRC equ SCCBase+$44 ; [W] Zähler für Retransmissionen
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SCC{NAME}_MFLR equ SCCBase+$46 ; [W] Maximalrahmenlänge
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SCC{NAME}_MAX_cnt equ SCCBase+$48 ; [W] Längenzähler
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SCC{NAME}_RFTHR equ SCCBase+$4a ; [W] Schwelle für empfangene Rahmenzahl
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SCC{NAME}_RFCNT equ SCCBase+$4c ; [W] empfangene Rahmen
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SCC{NAME}_HMASK equ SCCBase+$4e ; [W] Adreßmaske
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SCC{NAME}_HADDR1 equ SCCBase+$50 ; [W] Adressen
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SCC{NAME}_HADDR2 equ SCCBase+$52 ; [W]
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SCC{NAME}_HADRR3 equ SCCBase+$54 ; [W]
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SCC{NAME}_HADDR4 equ SCCBase+$56 ; [W]
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SCC{NAME}_TMP equ SCCBase+$58 ; [W] Temporärspeicher
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SCC{NAME}_TMP_MB equ SCCBase+$5a ; [W] "
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SCC{NAME}_CRCC equ SCCBase+$34 ; [L] --BISYNC-- temp. Wert CRC
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SCC{NAME}_PRCRC equ SCCBase+$38 ; [W] Empfangs-Vorgabe-CRC
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SCC{NAME}_PTCRC equ SCCBase+$3a ; [W] Sende-Vorgabe-CRC
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SCC{NAME}_B_PAREC equ SCCBase+$3c ; [W] Zähler Empfangs-Paritäts-Fehler
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SCC{NAME}_BSYNC equ SCCBase+$3e ; [W] SYNC-Zeichen
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SCC{NAME}_BDLE equ SCCBase+$40 ; [W] DLE-Zeichen
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SCC{NAME}_B_CHARACTER1 equ SCCBase+$42 ; [W] Steuerzeichen
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SCC{NAME}_B_CHARACTER2 equ SCCBase+$44 ; [W]
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SCC{NAME}_B_CHARACTER3 equ SCCBase+$46 ; [W]
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SCC{NAME}_B_CHARACTER4 equ SCCBase+$48 ; [W]
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SCC{NAME}_B_CHARACTER5 equ SCCBase+$4a ; [W]
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SCC{NAME}_B_CHARACTER6 equ SCCBase+$4c ; [W]
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SCC{NAME}_B_CHARACTER7 equ SCCBase+$4e ; [W]
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SCC{NAME}_B_CHARACTER8 equ SCCBase+$50 ; [W]
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SCC{NAME}_B_RCCM equ SCCBase+$52 ; [W] Empfangssteuerzeichenmaske
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SCC{NAME}_CRC_P equ SCCBase+$30 ; [L] --Transparent-- CRC-Vorgabe
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SCC{NAME}_CRC_C equ SCCBase+$34 ; [L] CRC-Konstante
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SCC{NAME}_E_C_PRES equ SCCBase+$30 ; [L] --Ethernet-- CRC-Vorgabe
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SCC{NAME}_E_C_MASK equ SCCBase+$34 ; [L] CRC-Maske
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SCC{NAME}_E_CRCEC equ SCCBase+$38 ; [L] CRC-Fehlerzähler
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SCC{NAME}_ALEC equ SCCBase+$3c ; [L] Alignment-Fehlerzähler
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SCC{NAME}_E_DISFC equ SCCBase+$40 ; [L] Zähler verworfene Rahmen
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SCC{NAME}_PADS equ SCCBase+$44 ; [W] Padding-Zeichen kurze Rahmen
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SCC{NAME}_RET_Lim equ SCCBase+$46 ; [W] Maximalzahl Retries
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SCC{NAME}_RET_cnt equ SCCBase+$48 ; [W] Momentanzahl Retries
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SCC{NAME}_E_MFLR equ SCCBase+$4a ; [W] Maximalrahmenlänge
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SCC{NAME}_MINFLR equ SCCBase+$4c ; [W] Minimalrahmenlänge
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SCC{NAME}_MAXD1 equ SCCBase+$4e ; [W] Maximallänge DMA1
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SCC{NAME}_MAXD2 equ SCCBase+$50 ; [W] Maximallänge DMA2
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SCC{NAME}_MAXD equ SCCBase+$52 ; [W] Rx Max DMA
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SCC{NAME}_DMA_cnt equ SCCBase+$54 ; [W] DMA-Zähler Empfang
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SCC{NAME}_MAX_b equ SCCBase+$56 ; [W] Max BD Byte Count
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SCC{NAME}_GADDR1 equ SCCBase+$58 ; [W] Group Address Filter
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SCC{NAME}_GADDR2 equ SCCBase+$5a ; [W]
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SCC{NAME}_GADDR3 equ SCCBase+$5c ; [W]
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SCC{NAME}_GADDR4 equ SCCBase+$5e ; [W]
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SCC{NAME}_TBUF0.data0 equ SCCBase+$60 ; [L] Save Areas - current frame
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SCC{NAME}_TBUF0.data1 equ SCCBase+$64 ; [L]
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SCC{NAME}_TBUF0.rba0 equ SCCBase+$68 ; [L]
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SCC{NAME}_TBUF0.crc equ SCCBase+$6c ; [L]
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SCC{NAME}_TBUF0.bcnt equ SCCBase+$70 ; [W]
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SCC{NAME}_PADDR1_H equ SCCBase+$72 ; [W] phys. Adresse
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SCC{NAME}_PADDR1_M equ SCCBase+$74 ; [W]
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SCC{NAME}_PADDR1_L equ SCCBase+$76 ; [W]
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SCC{NAME}_P_Per equ SCCBase+$78 ; [W] Persistenz
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SCC{NAME}_RFBD_ptr equ SCCBase+$7a ; [W] Rx First BD Counter
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SCC{NAME}_TFBD_ptr equ SCCBase+$7c ; [W] Tx First BD Pointer
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SCC{NAME}_TLBD_ptr equ SCCBase+$7e ; [W] Tx Last BD Pointer
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SCC{NAME}_TBUF1.data0 equ SCCBase+$80 ; [L] Save Areas - next frame
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SCC{NAME}_TBUF1.data1 equ SCCBase+$84 ; [L]
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SCC{NAME}_TBUF1.rba0 equ SCCBase+$88 ; [L]
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SCC{NAME}_TBUF1.crc equ SCCBase+$8c ; [L]
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SCC{NAME}_TBUF1.bcnt equ SCCBase+$90 ; [W]
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SCC{NAME}_TX_len equ SCCBase+$92 ; [W] Tx Frame Length Counter
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SCC{NAME}_IADDR1 equ SCCBase+$94 ; [W] Individual address filters
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SCC{NAME}_IADDR2 equ SCCBase+$96 ; [W]
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SCC{NAME}_IADDR3 equ SCCBase+$98 ; [W]
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SCC{NAME}_IADDR4 equ SCCBase+$9a ; [W]
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SCC{NAME}_BOFF_CNT equ SCCBase+$9c ; [W] Backoff Zähler
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SCC{NAME}_TADDR_H equ SCCBase+$9e ; [W] temp. Adresse
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SCC{NAME}_TADDR_M equ SCCBase+$9a ; [W]
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SCC{NAME}_TADDR_L equ SCCBase+$a0 ; [W]
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endm
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__defscc "1",RegBase+$0600,SCC1Base
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__defscc "2",RegBase+$0620,SCC2Base
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__defscc "3",RegBase+$0640,SCC3Base
|
|
__defscc "4",RegBase+$0660,SCC4Base
|
|
|
|
;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
; SMC:
|
|
|
|
SMC1Base equ RAMBase+$0e80
|
|
SMC2Base equ RAMBase+$0f80
|
|
|
|
__defsmc macro NAME,Adr,SMCBase
|
|
SMCMR{NAME} equ Adr+0 ; [W] Transparentmodus
|
|
SMCE{NAME} equ Adr+4 ; [B] Ereignisregister
|
|
SMCM{NAME} equ Adr+8 ; [W] Modus
|
|
SMC{NAME}_RBASE equ SMCBase+$00 ; [W] Empfangspufferdeskriptoradresse
|
|
SMC{NAME}_TBASE equ SMCBase+$02 ; [W] Sendepufferdeskriptoradresse
|
|
SMC{NAME}_RFCR equ SMCBase+$04 ; [B] Empfangs-Funktionscode
|
|
SMC{NAME}_TFCR equ SMCBase+$05 ; [B] Sende-Funktionscode
|
|
SMC{NAME}_MRBLR equ SMCBase+$06 ; [W] Maximallänge Empfangspuffer
|
|
SMC{NAME}_RSTATE equ SMCBase+$08 ; [L] interner Empfängerstatus
|
|
SMC{NAME}_RBPTR equ SMCBase+$10 ; [W] Rx Buffer descriptor pointer
|
|
SMC{NAME}_TSTATE equ SMCBase+$18 ; [L] interner Senderstatus
|
|
SMC{NAME}_TBPTR equ SMCBase+$20 ; [W] Tx Buffer Descriptor Pointer
|
|
SMC{NAME}_MAX_IDL equ SMCBase+$28 ; [W] --UART-- MAximalzahl Idle-Zeichen
|
|
SMC{NAME}_IDLC equ SMCBase+$28 ; [W] Idle-Zähler
|
|
SMC{NAME}_BRKLN equ SMCBase+$28 ; [W] Länge letztes Break-Zeichen
|
|
SMC{NAME}_BRKEC equ SMCBase+$28 ; [W] Receive Break Condition Counter
|
|
SMC{NAME}_BRKCR equ SMCBase+$28 ; [W] Sende-Break-Zähler
|
|
SMC{NAME}_R_mask equ SMCBase+$28 ; [W] temp. Bitmaske
|
|
SMC{NAME}_M_RxBD equ SMCBase+$00 ; [W] --GCI-- Monitor Channel Rx
|
|
SMC{NAME}_M_TxBD equ SMCBase+$02 ; [W] Monitor Channel Tx
|
|
SMC{NAME}_CI_RxBD equ SMCBase+$04 ; [W] C/I Channel Rx
|
|
SMC{NAME}_CI_TxBD equ SMCBase+$06 ; [W] C/I Channel Tx
|
|
SMC{NAME}_M_RxD equ SMCBase+$0c ; [W] Monitor Rx Data
|
|
SMC{NAME}_M_TxD equ SMCBase+$0e ; [W] Monitor Tx Data
|
|
SMC{NAME}_CI_RxD equ SMCBase+$10 ; [W] C/I Rx Data
|
|
SMC{NAME}_CI_TxD equ SMCBase+$12 ; [W] C/I Tx Data
|
|
endm
|
|
__defsmc "1",RegBase+$0682,SMC1Base
|
|
__defsmc "2",RegBase+$0692,SMC2Base
|
|
|
|
;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
; SPI:
|
|
|
|
SPIBase equ RAMBase+$0d80
|
|
|
|
SPMODE equ RegBase+$06a0 ; [W] Modusregister
|
|
SPIE equ RegBase+$06a6 ; [B] Ereignisregister
|
|
SPIM equ RegBase+$06aa ; [B] Maskenregister
|
|
SPICOM equ RegBase+$06ad ; [B] Kommandoregister
|
|
SPI_RBASE equ SPIBase+$00 ; [W] Empfangsdeskriptoradresse
|
|
SPI_TBASE equ SPIBase+$02 ; [W] Sendedeskriptoradresse
|
|
SPI_RFCR equ SPIBase+$04 ; [B] Empfangsfunktionscode
|
|
SPI_TFCR equ SPIBase+$05 ; [B] Sendefunktionscode
|
|
SPI_MRBLR equ SPIBase+$06 ; [W] Maximallänge Empfangspuffer
|
|
SPI_RSTATE equ SPIBase+$08 ; [L] Empfängerstatus
|
|
SPI_RBPTR equ SPIBase+$10 ; [W] mom. aktiver Empfangsdeskriptor
|
|
SPI_TSTATE equ SPIBase+$18 ; [L] Senderstatus
|
|
SPI_TBPTR equ SPIBase+$20 ; [W] mom. aktiver Sendedeskriptor
|
|
|
|
;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
; PIP:
|
|
|
|
PIPBase equ SMC2Base
|
|
|
|
PIPC equ RegBase+$06b2 ; [W] Konfigurationsregister
|
|
PTPR equ RegBase+$06b6 ; [W] Timing-Parameter
|
|
PIPE equ SMCE2 ; [B] Ereignisregister, überlagert!!
|
|
PBDIR equ RegBase+$06b8 ; [L] Datenrichtungsregister Port B
|
|
PBPAR equ RegBase+$06bc ; [L] Zuordnung Port B
|
|
PBODR equ RegBase+$06c2 ; [W] Steuerbits Port B als open drain
|
|
PBDAT equ RegBase+$06c4 ; [L] Datenregister Port B
|
|
PIP_RBASE equ PIPBase+$00 ; [W] Empfangsdeskriptoradresse
|
|
PIP_TBASE equ PIPBase+$02 ; [W] Sendedeskriptoradresse
|
|
PIP_CFCR equ PIPBase+$04 ; [B] Funktionscode
|
|
PIP_SMASK equ PIPBase+$05 ; [B] Statusmaske
|
|
PIP_MRBLR equ PIPBase+$06 ; [W] Maximallänge Empfangspuffer
|
|
PIP_RSTATE equ PIPBase+$08 ; [L] Empfängerstatus
|
|
PIP_R_PTR equ PIPBase+$0c ; [L] int. Empfangsdatenzeiger
|
|
PIP_RBPTR equ PIPBase+$10 ; [W] mom. Empfangsdeskriptor
|
|
PIP_R_CNT equ PIPBase+$12 ; [W] Empfangs-Byte-Zähler
|
|
PIP_RTEMP equ PIPBase+$14 ; [L] temp. Speicher
|
|
PIP_TSTATE equ PIPBase+$18 ; [L] Senderstatus
|
|
PIP_T_PTR equ PIPBase+$1c ; [L] mom. Sendedatenzeiger
|
|
PIP_TBPTR equ PIPBase+$20 ; [W] mom. Sendedeskriptor
|
|
PIP_T_CNT equ PIPBase+$22 ; [W] Sende-Byte-Zähler
|
|
PIP_TTEMP equ PIPBase+$24 ; [L] temp. Speicher
|
|
PIP_MAX_SL equ PIPBase+$28 ; [W] max. Ruhezeit
|
|
PIP_SL_CNT equ PIPBase+$2a ; [W] Ruhezähler
|
|
PIP_CHARACTER1 equ PIPBase+$2c ; [W] Steuerzeichen
|
|
PIP_CHARACTER2 equ PIPBase+$2e
|
|
PIP_CHARACTER3 equ PIPBase+$30
|
|
PIP_CHARACTER4 equ PIPBase+$32
|
|
PIP_CHARACTER5 equ PIPBase+$34
|
|
PIP_CHARACTER6 equ PIPBase+$36
|
|
PIP_CHARACTER7 equ PIPBase+$38
|
|
PIP_CHARACTER8 equ PIPBase+$3a
|
|
PIP_RCCM equ PIPBase+$3c ; [W] Steuerzeichenmaske
|
|
PIP_RCCR equ PIPBase+$3e ; [W] Steuerzeichenregister
|
|
|
|
;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
; SI:
|
|
|
|
SIMODE equ RegBase+$06e0 ; [L] Modus serielles Interface
|
|
SIGMR equ RegBase+$06e4 ; [B] globale Moduseinstellung
|
|
SISTR equ RegBase+$06e6 ; [B] Adresse Router-RAM
|
|
SICMR equ RegBase+$06e7 ; [B] Kommandoregister serielles Interface
|
|
SICR equ RegBase+$06ec ; [L] Taktverteilung serielles Interface
|
|
SIRP equ RegBase+$06f2 ; [L] RAM-Zeiger
|
|
SIRAM equ RegBase+$0700 ; [ ] Routing-RAM
|
|
|
|
;=============================================================================
|
|
|
|
case "68340"
|
|
|
|
;-----------------------------------------------------------------------------
|
|
; die Kommentare fallen hier evtl. etwas spartanischer aus, weil der Technical
|
|
; Summary von Motorola für den 68340 noch nicht so ins Detail geht.
|
|
|
|
SIMBAR equ $0003ff00 ; [L] Einstellung Peripherieadressen
|
|
|
|
MCR equ SIMBase+$000 ; [W] Modulkonfiguration SIM
|
|
|
|
SYNCR equ SIMBase+$004 ; [W] Steuerung Taktfrequenz-Synthi
|
|
AVR equ SIMBase+$006 ; [B] Auto-Vektoren
|
|
RSR equ SIMBase+$007 ; [B] Reset Status
|
|
|
|
PORTA equ SIMBase+$011 ; [B] Datenregister Port A
|
|
DDRA equ SIMBase+$013 ; [B] Datenrichtungsregister Port A
|
|
PPRA1 equ SIMBase+$015 ; [B] Festlegung der Funktionen der...
|
|
PPRA2 equ SIMBase+$017 ; [B] ...Leitungen von Port A
|
|
PORTB equ SIMBase+$019 ; [B] Datenregister Port B
|
|
PORTB1 equ SIMBase+$01b ; [B] dito
|
|
DDRB equ SIMBase+$01d ; [B] Datenrichtungsregister Port B
|
|
PPRARB equ SIMBase+$01f ; [B] Festlegung Port B-Leitungen
|
|
SWIV equ SIMBase+$020 ; [B] Software-Vektoren
|
|
SYPCR equ SIMBase+$021 ; [B] Systemschutz
|
|
PICR equ SIMBase+$022 ; [W] Steuerung PIT
|
|
PITR equ SIMBase+$024 ; [W] Datenregister PIT
|
|
SWSR equ SIMBase+$027 ; [B] Software Service
|
|
|
|
;-----------------------------------------------------------------------------
|
|
; Chip Selects:
|
|
|
|
__cnt set 0
|
|
rept 4
|
|
__name set "\{__CNT}"
|
|
CS{__name}AM1 set SIMBase+$040+__cnt*8 ; [W] Adressmaske 1 CSn
|
|
CS{__name}AM2 set SIMBase+$042+__cnt*8 ; [W] Adressmaske 2 CSn
|
|
CS{__name}BA1 set SIMBase+$044+__cnt*8 ; [W] Basisadresse 1 CSn
|
|
CS{__name}BA2 set SIMBase+$046+__cnt*8 ; [W] Basisadresse 2 CSn
|
|
__cnt set __cnt+1
|
|
endm
|
|
|
|
;-----------------------------------------------------------------------------
|
|
; DMA:
|
|
|
|
DMABase equ SIMBase+$780
|
|
DMAMCR1 equ DMABase+$000 ; [W] Modulkonfiguration DMA-Kanal 1
|
|
DMAINTR1 equ DMABase+$004 ; [W] Interrupts DMA-Kanal 1
|
|
DMACCR1 equ DMABase+$008 ; [W] Steuerregister DMA-Kanal 1
|
|
DMACSR1 equ DMABase+$00a ; [B] Statusregister DMA-Kanal 1
|
|
DMAFCR1 equ DMABase+$00b ; [B] Funktionscoderegister DMA-Kanal 1
|
|
DMASAR1 equ DMABase+$00c ; [L] Quelladresse DMA-Kanal 1
|
|
DMADAR1 equ DMABase+$010 ; [L] Zieladresse DMA-Kanal 1
|
|
DMABTC1 equ DMABase+$014 ; [L] Bytezähler DMA-Kanal 1
|
|
DMAMCR2 equ DMABase+$020 ; Kanal 2 genauso, nur $20 weiter
|
|
DMAINTR2 equ DMABase+$024
|
|
DMACCR2 equ DMABase+$028
|
|
DMACSR2 equ DMABase+$02a
|
|
DMAFCR2 equ DMABase+$02b
|
|
DMASAR2 equ DMABase+$02c
|
|
DMADAR2 equ DMABase+$030
|
|
DMABTC2 equ DMABase+$034
|
|
|
|
;-----------------------------------------------------------------------------
|
|
; serielles:
|
|
|
|
SMBase equ SIMBase+$700
|
|
SMMCR equ SMBase+$000 ; [W] Modulkonfiguration SM
|
|
SMILR equ SMBase+$004 ; [B] Interruptebene
|
|
SMIVR equ SMBase+$005 ; [B] Interruptvektor
|
|
SMIPCR equ SMBase+$014 ; [BR] Anzeige, ob Pegelwechsel an Leitungen
|
|
SMACR equ SMBase+$014 ; [BW] Hilfssteuerregister
|
|
SMISR equ SMBase+$015 ; [BR] Interruptanzeigen
|
|
SMIER equ SMBase+$015 ; [BW] Interuptfreigaben
|
|
SMOPCR equ SMBase+$01d ; [BW] Steuerung Ausgabeports
|
|
SMIP equ SMBase+$01d ; [BR] Status Eingabeports
|
|
SMOPS equ SMBase+$01e ; [BW] Portbits einzeln setzen
|
|
SMOPR equ SMBase+$01f ; [BW] Portbits einzeln zurücksetzen
|
|
SMMR1A equ SMBase+$010 ; [B] Modusregister 1 Kanal A
|
|
SMMR2A equ SMBase+$020 ; [B] Modusregister 2 Kanal A
|
|
SMCSRA equ SMBase+$011 ; [BR] Taktauswahl Kanal A
|
|
SMSRA equ SMBase+$011 ; [BW] Statusregister Kanal A
|
|
SMCRA equ SMBase+$012 ; [BW] Kommandoregister Kanal A
|
|
SMRBA equ SMBase+$013 ; [BR] Empfangsdatenregister Kanal A
|
|
SMTBA equ SMBase+$013 ; [BW] Sendedatenregister Kanal A
|
|
SMMR1B equ SMBase+$018 ; [B] Modusregister 1 Kanal B
|
|
SMMR2B equ SMBase+$021 ; [B] Modusregister 2 Kanal B
|
|
SMCSRB equ SMBase+$019 ; [BR] Taktauswahl Kanal B
|
|
SMSRB equ SMBase+$019 ; [BW] Statusregister Kanal B
|
|
SMCRB equ SMBase+$01a ; [BW] Kommandoregister Kanal B
|
|
SMRBB equ SMBase+$01b ; [BR] Empfangsdatenregister Kanal B
|
|
SMTBB equ SMBase+$01b ; [BW] Sendedatenregister Kanal B
|
|
|
|
;-----------------------------------------------------------------------------
|
|
; Timer:
|
|
|
|
TMBase equ SIMBase+$600
|
|
TM1MCR equ TMBase+$000 ; [W] Modulkonfiguration Timer 1
|
|
TM1IR equ TMBase+$004 ; [W] Interruptkonfiguration Timer 1
|
|
TM1CR equ TMBase+$006 ; [W] Steuerung Timer 1
|
|
TM1SR equ TMBase+$008 ; [W] Status/Vorteiler Timer 1
|
|
TM1CNTR equ TMBase+$00a ; [W] Zählregister Timer 1
|
|
TM1PREL1 equ TMBase+$00c ; [W] Vorbelegung 1 Timer 1
|
|
TM1PREL2 equ TMBase+$00e ; [W] Vorbelegung 2 Timer 1
|
|
TM1COM equ TMBase+$010 ; [W] Vergleichsregister Timer 1
|
|
TM2MCR equ TMBase+$040 ; dito Kanal 2
|
|
TM2IR equ TMBase+$044
|
|
TM2CR equ TMBase+$046
|
|
TM2SR equ TMBase+$048
|
|
TM2CNTR equ TMBase+$04a
|
|
TM2PREL1 equ TMBase+$04c
|
|
TM2PREL2 equ TMBase+$04e
|
|
TM2COM equ TMBase+$050
|
|
|
|
;=============================================================================
|
|
; ab hier 68332-Register
|
|
|
|
case "68332"
|
|
|
|
;-----------------------------------------------------------------------------
|
|
; die fundamentalen SIM-Steuerregister
|
|
|
|
SIMCR equ SIMBase+$00 ; [W] MCU-Konfiguration
|
|
SIYPCR equ SIMBase+$21 ; [W] Watchdog, Bus-Monitorsteuerung
|
|
SWSR equ SIMBase+$27 ; [B] Watchdog zurücksetzen (mit $55/$aa)
|
|
PICR equ SIMBase+$22 ; [W] Interruptsteuerung Timer
|
|
PITR equ SIMBase+$24 ; [W] Zählwert Timer
|
|
|
|
;-----------------------------------------------------------------------------
|
|
; der Synthesizer für den Prozessortakt
|
|
|
|
SYNCR equ SIMBase+$04 ; [W] Taktfrequenz-Synthesizer-Steuerung
|
|
|
|
;-----------------------------------------------------------------------------
|
|
; die Chip-Select-Ausgänge
|
|
|
|
CSPAR0 equ SIMBase+$44 ; [W] Steuerung der Ausgänge CSBOOT,CS0..CS5
|
|
CSPAR1 equ SIMBase+$46 ; [W] Steuerung der Ausgänge CS6..CS10
|
|
CSBARBT equ SIMBase+$48 ; [W] Startadresse Boot-ROM
|
|
CSORBT equ SIMBase+$4a ; [W] Optionen Boot-ROM
|
|
__cnt set 0
|
|
rept 10 ; nur 0..9 so erzeugen, damit keine Hex-Namen
|
|
__name set "\{__CNT}"
|
|
CSBAR{__name} equ SIMBase+$4c+__cnt*4 ; [W] Startadresse CSn
|
|
CSOR{__name} equ SIMBase+$4e+__cnt*4 ; [W] Optionen CSn
|
|
__cnt set __cnt+1
|
|
endm
|
|
CSBAR10 equ SIMBase+$74 ; [W] Startadresse CS10
|
|
CSOR10 equ SIMBase+$76 ; [W] Optionen CS10
|
|
|
|
;-----------------------------------------------------------------------------
|
|
; Nutzung der SIM-Bits als einfache I/O-Ports
|
|
|
|
PORTC equ SIMBase+$41 ; [B] Datenbits Port C
|
|
PORTE0 equ SIMBase+$11 ; [B] Datenbits Port E
|
|
PORTE1 equ SIMBase+$13 ; [B] dito
|
|
DDRE equ SIMBase+$15 ; [B] Datenrichtungsbits Port E
|
|
PEPAR equ SIMBase+$17 ; [B] Steuerung Port E-Pins als Ports oder Bussignale
|
|
PORTF0 equ SIMBase+$19 ; [B] Datenbits Port F
|
|
PORTF1 equ SIMBase+$1b ; [B] dito
|
|
DDRF equ SIMBase+$1d ; [B] Datenrichtungsbits Port F
|
|
PFPAR equ SIMBase+$1f ; [B] Steuerung Port F-Pins als Ports oder Bussignale
|
|
|
|
;-----------------------------------------------------------------------------
|
|
; Register für den Boundary-Scan-Test des SIM (for Motorola use only...)
|
|
|
|
SIMTR equ SIMBase+$02 ; [W] Testregister SIM
|
|
SIMTRE equ SIMBase+$08 ; [W] Testregister E-Takt
|
|
TSTMSRA equ SIMBase+$30 ; [W] Schieberegister A (Boundary Scan)
|
|
TSTMSRB equ SIMBase+$32 ; [W] Schieberegister B (Boundary Scan)
|
|
TSTSC equ SIMBase+$34 ; [W] Register Schiebezahl
|
|
TSTRC equ SIMBase+$36 ; [W] Register Wiederholungszahl
|
|
CREG equ SIMBase+$38 ; [W] Steuerregister Boundary Scan
|
|
DREG equ SIMBase+$3a ; [W] verteiltes Register (?!)
|
|
|
|
;-----------------------------------------------------------------------------
|
|
; programmierbare Zeitgeber:
|
|
|
|
TPUBase equ SIMBase+$400 ; Basisadresse TPU-Registersatz
|
|
TPUMCR equ TPUBase+$00 ; [W] Basiskonfiguration TPU
|
|
TICR equ TPUBase+$08 ; [W] Interruptsteuerung TPU
|
|
CIER equ TPUBase+$0a ; [W] TPU Interrupt-Freigaben
|
|
CISR equ TPUBase+$20 ; [W] TPU Interrupt-Anzeigen
|
|
CFSR0 equ TPUBase+$0c ; [W] TPU Betriebsarten Kanal 12..15
|
|
CFSR1 equ TPUBase+$0e ; [W] TPU Betriebsarten Kanal 8..11
|
|
CFSR2 equ TPUBase+$10 ; [W] TPU Betriebsarten Kanal 4.. 7
|
|
CFSR3 equ TPUBase+$12 ; [W] TPU Betriebsarten Kanal 0.. 3
|
|
HSQR0 equ TPUBase+$14 ; [W] TPU Sub-Betriebsarten Kanal 8..15
|
|
HSQR1 equ TPUBase+$16 ; [W] TPU Sub-Betriebsarten Kanal 0.. 7
|
|
HSRR0 equ TPUBase+$18 ; [W] TPU Service-Anfragebits Kanal 8..15
|
|
HSRR1 equ TPUBase+$1a ; [W] TPU Service-Anfragebits Kanal 0.. 7
|
|
CPR0 equ TPUBase+$1c ; [W] TPU Priorität Kanal 8..15
|
|
CPR1 equ TPUBase+$1e ; [W] TPU Priorität Kanal 0.. 7
|
|
DSCR equ TPUBase+$04 ; [W] Register für Entwicklung und Test ?!
|
|
DSSR equ TPUBase+$06 ; eine genauere Beschreibung habe ich
|
|
LR equ TPUBase+$22 ; leider nicht...
|
|
SGLR equ TPUBase+$24 ;
|
|
DCNR equ TPUBase+$26 ;
|
|
TCR equ TPUBase+$02 ;
|
|
|
|
;-----------------------------------------------------------------------------
|
|
; das Kommando-RAM für die TPU:
|
|
|
|
TPURAMBase equ SIMBase+$100 ; Basisadresse TPURAM-Steuerregister
|
|
TRAMMCR equ TPURAMBase+$00 ; [B] Basiskonfiguration TPURAM
|
|
TRAMTST equ TPURAMBase+$02 ; [W] Testregister TPURAM
|
|
TRAMBAR equ TPURAMBase+$04 ; [W] Basisadresse TPURAM
|
|
|
|
;-----------------------------------------------------------------------------
|
|
; serielles:
|
|
|
|
QSMBase equ SIMBase+$200 ; Basisadresse serielle E/A-Einheit
|
|
QSMCR equ QSMBase+$00 ; [W] Basiskonfiguration QSM
|
|
QTEST equ QSMBase+$02 ; [W] QSM Testregister
|
|
QILR equ QSMBase+$04 ; [B] QSM Interruptprioritäten
|
|
QIVR equ QSMBase+$05 ; [B] QSM Interruptvektor
|
|
PORTQS equ QSMBase+$14 ; [W] Datenbits QSM paralleler Port
|
|
PQSPAR equ QSMBase+$16 ; [B] Umschaltung Portbits QSM/paralleler Port
|
|
DDRQS equ QSMBase+$17 ; [B] Datenrichtungsregister Port QSM
|
|
SPCR0 equ QSMBase+$18 ; [W] Steuerregister 0 QSPI
|
|
SPCR1 equ QSMBase+$1a ; [W] Steuerregister 1 QSPI
|
|
SPCR2 equ QSMBase+$1c ; [W] Steuerregister 2 QSPI
|
|
SPCR3 equ QSMBase+$1e ; [B] Steuerregister 3 QSPI
|
|
SPSR equ QSMBase+$1f ; [B] Statusregister QSPI
|
|
__cnt set 0 ; Definition QSPI-RAM
|
|
rept 16
|
|
__name set "\{__CNT}"
|
|
RR{__name} equ QSMBase+$100+__cnt*2 ; [W] Daten-RAM Empfangsseite
|
|
TR{__name} equ QSMBase+$120+__cnt*2 ; [W] Daten-RAM Sendeseite
|
|
CR{__name} equ QSMBase+$140+__cnt ; [B] Befehls-RAM
|
|
__cnt set __cnt+1
|
|
endm
|
|
SCCR0 equ QSMBase+$08 ; [W] Steuerregister 0 SCI
|
|
SCCR1 equ QSMBase+$0a ; [W] Steuerregister 1 SCI
|
|
SCSR equ QSMBase+$0c ; [W] Statusregister SCI
|
|
SCDR equ QSMBase+$0e ; [W] Datenregister SCI
|
|
|
|
;-----------------------------------------------------------------------------
|
|
|
|
endcase ; von Prozessorunterscheidung
|
|
|
|
endif ; von ifdef ...
|
|
|
|
restore ; wieder erlauben
|
|
|
|
|