128 lines
5.4 KiB
PHP
128 lines
5.4 KiB
PHP
save
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listing off ; kein Listing über diesen File
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;****************************************************************************
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;* *
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;* AS 1.41 - Datei REG29K.INC *
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;* *
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;* Sinn : enthält Adreßdefinitionen für die 2924x-Prozessoren *
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;* *
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;* letzte Änderungen : 20. 7.1995 *
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;* *
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;****************************************************************************
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ifndef reg29kinc ; verhindert Mehrfacheinbindung
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reg29kinc equ 1
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if (MOMCPU<>168512)&&(MOMCPU<>168515)&&(MOMCPU<>168517)
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fatal "Falscher Prozessortyp eingestellt: nur AM29240, AM29243 oder AM29245 erlaubt!"
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endif
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if MOMPASS=1
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message "AM2924x-SFR-Definitionen (C) 1995 Alfred Arnold"
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message "binde AM\{MOMCPU}-SFRs ein"
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endif
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;----------------------------------------------------------------------------
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; Registerbasis
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RegBase equ 0x80000000
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;----------------------------------------------------------------------------
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; ROM-Controller
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RMCT equ RegBase+0x00 ; ROM-Steuerregister
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RMCF equ RegBase+0x04 ; ROM-Konfigurationsregister
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;----------------------------------------------------------------------------
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; DRAM-Controller
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DRCT equ RegBase+0x08 ; DRAM-Steuerregister
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DRCF equ RegBase+0x0c ; DRAM-Konfigurationsregister
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;----------------------------------------------------------------------------
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; PIA
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PICT0 equ RegBase+0x20 ; PIA Steuerregister 0
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PICT1 equ RegBase+0x24 ; PIA Steuerregister 1
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;----------------------------------------------------------------------------
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; DMA-Controller
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DMCT0 equ RegBase+0x30 ; Steuerregister Kanal 0
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DMAD0 equ RegBase+0x34 ; Adreßregister Kanal 0
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TAD0 equ RegBase+0x70 ; Queued-Adreßregister Kanal 0
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DMCN0 equ RegBase+0x38 ; Zählregister Kanal 0
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TCN0 equ RegBase+0x3c ; Queued-Zählregister Kanal 0
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DMCT1 equ RegBase+0x40 ; Steuerregister Kanal 1
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DMAD1 equ RegBase+0x44 ; Adreßregister Kanal 1
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TAD1 equ RegBase+0x74 ; Queued-Adreßregister Kanal 1
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DMCN1 equ RegBase+0x48 ; Zählregister Kanal 1
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TCN1 equ RegBase+0x4c ; Queued-Zählregister Kanal 1
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if MOMCPU<>0x29245
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DMCT2 equ RegBase+0x50 ; Steuerregister Kanal 2
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DMAD2 equ RegBase+0x54 ; Adreßregister Kanal 2
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TAD2 equ RegBase+0x78 ; Queued-Adreßregister Kanal 2
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DMCN2 equ RegBase+0x58 ; Zählregister Kanal 2
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TCN2 equ RegBase+0x5c ; Queued-Zählregister Kanal 2
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DMCT3 equ RegBase+0x60 ; Steuerregister Kanal 3
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DMAD3 equ RegBase+0x64 ; Adreßregister Kanal 3
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TAD3 equ RegBase+0x7c ; Queued-Adreßregister Kanal 3
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DMCN3 equ RegBase+0x68 ; Zählregister Kanal 3
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TCN3 equ RegBase+0x6c ; Queued-Zählregister Kanal 3
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endif
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;----------------------------------------------------------------------------
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; PIO
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POCT equ RegBase+0xd0 ; PIO-Steuerregister
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PIN equ RegBase+0xd4 ; PIO-Eingangsregister
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POUT equ RegBase+0xd8 ; PIO-Ausgangsregister
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POEN equ RegBase+0xdc ; PIO-Richtungssteuerung
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;----------------------------------------------------------------------------
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; Parallelport
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PPCT equ RegBase+0xc0 ; Steuerregister
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PPST equ RegBase+0xc8 ; Statusrtegister
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PPDT equ RegBase+0xc4 ; Datenregister
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;----------------------------------------------------------------------------
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; serielle Ports
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SPCTA equ RegBase+0x80 ; Steuerregister Kanal A
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SPSTA equ RegBase+0x84 ; Statusregister Kanal A
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SPTHA equ RegBase+0x88 ; Senderegister Kanal A
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SPRBA equ RegBase+0x8c ; Empfangsregister Kanal A
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BAUDA equ RegBase+0x90 ; Baudratenregister Kanal A
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if MOMCPU<>0x29245
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SPCTB equ RegBase+0xa0 ; Steuerregister Kanal A
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SPSTB equ RegBase+0xa4 ; Statusregister Kanal A
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SPTHB equ RegBase+0xa8 ; Senderegister Kanal A
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SPRBB equ RegBase+0xac ; Empfangsregister Kanal A
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BAUDB equ RegBase+0xb0 ; Baudratenregister Kanal A
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endif
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;----------------------------------------------------------------------------
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; Video-Interface
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if MOMCPU<>0x29243
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VCT equ RegBase+0xe0 ; Steuerregister
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TOP equ RegBase+0xe4 ; Zeilennummer oberer Rand
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SIDE equ RegBase+0xe8 ; Spaltennummer linker/rechter Rand
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VDT equ RegBase+0xec ; Datenregister
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endif
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;----------------------------------------------------------------------------
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; Interrupt-Steuerung
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ICT equ RegBase+0x28 ; Steuerregister
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IMASK equ RegBase+0x2c ; Maskenregister
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endif
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restore
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