226 lines
10 KiB
PHP
226 lines
10 KiB
PHP
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save
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listing off ; kein Listing <EFBFBD>ber diesen File
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;****************************************************************************
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;* *
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;* AS 1.41 - Datei REG251.INC *
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;* *
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;* Sinn : enth<EFBFBD>lt SFR- und Bitdefinitionen f<EFBFBD>r MCS-251-Prozessoren *
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;* *
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;* letzte <EFBFBD>nderungen : 30.12.1995 *
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;* *
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;****************************************************************************
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ifndef reg251inc ; verhindert Mehrfacheinbindung
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reg251inc equ 1
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if MOMCPUNAME<>"80C251"
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fatal "Falscher Prozessortyp eingestellt: nur 80C251 erlaubt!"
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endif
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if MOMPASS=1
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message "MCS-251-SFR-Definitionen (C) 1995 Alfred Arnold"
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message "binde \{MOMCPU}-SFRs ein"
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endif
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;----------------------------------------------------------------------------
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; CPU-Kern:
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; ACC = A = R11
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; B = R10
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; SP/SPH = SPX = DR60
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; DPL/DPH/DPXL = DPX = DR56
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; CY wird von AS selbst benutzt
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ACC port 0e0h ; Akkumulator
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B port 0f0h ; B-Register
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PSW port 0d0h ; 8051-kompatibles PSW
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CARRY bit PSW.7 ; Carry
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AC bit PSW.6 ; Auxiliary-Carry
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F0 bit PSW.5 ; Flag 0
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RS1 bit PSW.4 ; Register-Bank-Auswahl
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RS0 bit PSW.3
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OV bit PSW.2 ; Overflow-Flag
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UD bit PSW.1 ; User-Flag
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P bit PSW.0 ; Parity-Flag
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PSW1 port 0d1h ; erweitertes PSW (Bits 2-4,6-7 wie in PSW)
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N bit PSW1.5 ; Negatives Ergebnis?
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Z bit PSW1.1 ; Ergebnis 0 ?
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SP port 81h ; Stackpointer (Bit 0..7)
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SPH port 0bdh ; Stackpointer (Bit 8..15)
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DPL port 082h ; Datenzeiger (Bit 0..7)
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DPH port 083h ; Datenzeiger (Bit 8..15)
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DPXL port 084h ; Datenzeiger (Bit 15..23)
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PCON port 087h ; Power-Down-Modi u.a.
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SMOD1 bit PCON.7 ; Verdopplung Baudrate in Modus 1..3
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SMOD0 bit PCON.6 ; Umschaltung SCON.7 als FE/SM0
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POF bit PCON.4 ; war Spannung weg ?
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GF1 bit PCON.3 ; General Flag 1
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GF0 bit PCON.2 ; General Flag 0
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PD bit PCON.1 ; in Powerdown-Modus schalten
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IDL bit PCON.0 ; in Idle-Modus schalten
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IE port 0a8h ; Interrupt-Freigaben (eigentlich IE0,
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; aber das ist schon belegt
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EA bit IE.7 ; generelle Interruptsperre
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EC bit IE.6 ; PCA-Interrupts freigeben
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ET2 bit IE.5 ; Interrupts Timer 2 freigeben
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ES bit IE.4 ; Interrupts ser. Schnittstelle freigeben
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ET1 bit IE.3 ; Interrupt Timer 1 freigeben
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EX1 bit IE.2 ; externen Interrupt 1 freigeben
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ET0 bit IE.1 ; Interrupt Timer 0 freigeben
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EX0 bit IE.0 ; externen Interrupt 0 freigeben
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IPH0 port 0b7h ; Interrupt-Priorit<EFBFBD>ten
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IPL0 port 0b8h
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;----------------------------------------------------------------------------
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; Ports mit Extrafunktionen:
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P0 port 080h ; Port 0
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P1 port 090h ; Port 1
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T2 bit P1.0 ; Ein/Ausgabe Timer 2
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T2EX bit P1.1 ; Trigger Timer 2
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ECI bit P1.2 ; externer Takt PCA
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CEX0 bit P1.3 ; Ein/Ausgabe PCA-Modul 0
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CEX1 bit P1.4 ; Ein/Ausgabe PCA-Modul 1
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CEX2 bit P1.5 ; Ein/Ausgabe PCA-Modul 2
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CEX3 bit P1.6 ; Ein/Ausgabe PCA-Modul 3
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CEX4 bit P1.7 ; Ein/Ausgabe PCA-Modul 4
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P2 port 0a0h ; Port 2
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P3 port 0b0h ; Port 3
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RXD bit P3.0 ; serielle Empfangsleitung
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TXD bit P3.1 ; serielle Sendeleitung
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INT0 bit P3.2 ; externer Interrupt 0
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INT1 bit P3.3 ; externer Interrupt 1
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T0 bit P3.4 ; Takteingang Timer 0
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T1 bit P3.5 ; Takteingang Timer 1
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WR bit P3.6 ; Leseleitung
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RD bit P3.7 ; Schreibleitung
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;----------------------------------------------------------------------------
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; serieller Port:
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SCON port 098h ; Konfiguration
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FE bit SCON.7 ; fehlerhaftes Stopbit ?
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SM0 bit SCON.7 ; Modusauswahl
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SM1 bit SCON.6
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SM2 bit SCON.5
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REN bit SCON.4 ; Empf<EFBFBD>nger freigeben
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TB8 bit SCON.3 ; Sendedatenbit 8
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RB8 bit SCON.2 ; Empfangsdatenbit 8
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TI bit SCON.1 ; Zeichen vollst<EFBFBD>ndig versandt ?
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RI bit SCON.0 ; Zeichen vollst<EFBFBD>ndig empfangen ?
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SBUF port 099h ; Datenregister
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SADEN port 0b9h ; Slave-Adre<EFBFBD>maske
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SADDR port 0a9h ; Slave-Adresse
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;----------------------------------------------------------------------------
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; Z<EFBFBD>hler/Watchdog:
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TL0 port 08ah ; Z<EFBFBD>hlwert Z<EFBFBD>hler 0
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TH0 port 08ch
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TL1 port 08bh ; Z<EFBFBD>hlwert Z<EFBFBD>hler 1
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TH1 port 08dh
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TCON port 088h ; Steuerung Z<EFBFBD>hler 0/1
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TF1 bit TCON.7 ; <EFBFBD>berlauf Timer 1 ?
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TR1 bit TCON.6 ; Timer 1 starten/stoppen
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TF0 bit TCON.5 ; <EFBFBD>berlauf Timer 0 ?
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TR0 bit TCON.4 ; Timer 0 starten/stoppen
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IE1 bit TCON.3 ; externer Interrupt 1 augetreten ?
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IT1 bit TCON.2 ; Flanken/Pegeltriggerung ext. Interrupt 1
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IE0 bit TCON.1 ; externer Interrupt 0 augetreten ?
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IT0 bit TCON.0 ; Flanken/Pegeltriggerung ext. Interrupt 0
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TMOD port 089h ; Steuerung/Modus Z<EFBFBD>hler 0/1
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M00 bit TMOD.0 ; Modus Timer 0
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M10 bit TMOD.1
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CT0 bit TMOD.2 ; Z<EFBFBD>hler/Timerumschaltung Timer 0
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GATE0 bit TMOD.3 ; Freigabemodus Timer 0
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M01 bit TMOD.4 ; Modus Timer 1
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M11 bit TMOD.5
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CT1 bit TMOD.6 ; Z<EFBFBD>hler/Timerumschaltung Timer 1
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GATE1 bit TMOD.7 ; Freigabemodus Timer 1
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TL2 port 0cch ; Z<EFBFBD>hlwert Z<EFBFBD>hler 2
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TH2 port 0cdh
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T2CON port 0c8h ; Steuerung Z<EFBFBD>hler 2
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TF2 bit T2CON.7 ; <EFBFBD>berlauf Timer 2 ?
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EXF2 bit T2CON.6 ; Flanke an T2EX aufgetreten ?
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RCLK bit T2CON.5 ; Timer 2 oder 1 f<EFBFBD>r seriellen Empfangstakt nutzen ?
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TCLK bit T2CON.4 ; Timer 2 oder 1 f<EFBFBD>r seriellen Sendetakt nutzen ?
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EXEN2 bit T2CON.3 ; Fang durch T2EX freigeben
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TR2 bit T2CON.2 ; Timer 2 starten/stoppen
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CT2 bit T2CON.1 ; Z<EFBFBD>hler/Timerumschaltung Timer 2
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CPRL2 bit T2CON.0 ; Fang oder Neuladen durch T2EX
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T2MOD port 0c9h ; Steuerung/Modus Z<EFBFBD>hler 2
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T2OE bit T2MOD.1 ; Ausgabe Timer 2 an T2 freigeben
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DCEN bit T2MOD.0 ; Z<EFBFBD>hlrichtung Timer 2
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RCAP2L port 0cah ; Reload/Capture-Wert Timer 2
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RCAP2H port 0cbh
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WDTRST port 0a6h ; Watchdog zur<EFBFBD>cksetzen
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;----------------------------------------------------------------------------
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; Z<EFBFBD>hlerfeld:
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CCON port 0d8h ; Steuerregister
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CF bit CCON.7 ; <EFBFBD>berlauf PCA ?
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CR bit CCON.6 ; PCA-Timer starten/stoppen
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CCF4 bit CCON.4 ; Hat PCA-Modul 4..0 angesprochen ?
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CCF3 bit CCON.3
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CCF2 bit CCON.2
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CCF1 bit CCON.1
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CCF0 bit CCON.0
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CMOD port 0d9h ; Modusregister
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CIDL bit CMOD.7 ; PCA w<EFBFBD>hrend Idle-Mode abschalten
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WDTE bit CMOD.6 ; Watchdog-Ausgabe an PCA-Modul 4 freigeben
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CPS1 bit CMOD.2 ; PCA-Taktauswahl
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CPS0 bit CMOD.1
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ECF bit CMOD.0 ; Interruptfreigabe
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CL port 0e9h ; Z<EFBFBD>hlwert
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CH port 0f9h
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__defpcamodule macro Offset,NUM
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CCAPM{NUM} port 0d0h+Offset ; Modusregister
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ECOM{NUM} bit CCAPM0.6 ; Komparator Modul x einschalten
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CAPP{NUM} bit CCAPM0.5 ; Fangfunktion Modul x einschalten (pos. Flanke)
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CAPN{NUM} bit CCAPM0.4 ; Fangfunktion Modul x einschalten (neg. Flanke)
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MAT{NUM} bit CCAPM0.3 ; Interrupt bei Gleichheit Modul x einschalten
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TOG{NUM} bit CCAPM0.2 ; High-Speed-Output-Modus Modul x einschalten
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PWM{NUM} bit CCAPM0.1 ; PWM-Modus Modul x einschalten
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ECCF{NUM} bit CCAPM0.0 ; Interrupts durch CCFx einschalten
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CCAP{NUM}L port 0e0h+Offset ; Vergleichs/Fangwert Modul x
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CCAP{NUM}H port 0f0h+Offset
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endm
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__defpcamodule 0ah,"0"
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__defpcamodule 0bh,"1"
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__defpcamodule 0ch,"2"
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__defpcamodule 0dh,"3"
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__defpcamodule 0eh,"4"
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;----------------------------------------------------------------------------
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endif
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restore ; wieder erlauben
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