Commit Graph

112 Commits

Author SHA1 Message Date
kurtis.heimerl 187b03d847 uhd: cleanup startup timestamp alignment
At startup, instead of flushing initial packets blindly,
send a stop streaming command, flush, and start. The same
procedure is used in the event of a runtime timestamp
validity error.

Signed-off-by: Thomas Tsou <ttsou@vt.edu>

git-svn-id: http://wush.net/svn/range/software/public/openbts/trunk@2651 19bc5d8c-e614-43d4-8b26-e1612bc8e597
2011-11-26 03:17:40 +00:00
kurtis.heimerl 68292106af uhd: rework handling of timestamp errors
On a lapses of time monotonicity (and possibly other errors),
stop and restart the receive streaming with a buffer flush
in between. This is a cleaner replacement to the previous
clock reset with that didn't attempt to stop steaming.

Signed-off-by: Thomas Tsou <ttsou@vt.edu>

git-svn-id: http://wush.net/svn/range/software/public/openbts/trunk@2647 19bc5d8c-e614-43d4-8b26-e1612bc8e597
2011-11-26 03:17:28 +00:00
kurtis.heimerl c7cb817cb1 uhd: fix timestamp conversion bug on 32-bit architectures
Type size_t was used in the UHD time_spec_t to integer
conversion, which would overflow at roughly 4 and a half
hours causing the sample buffer to error on timestamp
validity. Builds where size_t takes on 64-bits were not
affected by this bug.

Signed-off-by: Thomas Tsou <ttsou@vt.edu>

git-svn-id: http://wush.net/svn/range/software/public/openbts/trunk@2646 19bc5d8c-e614-43d4-8b26-e1612bc8e597
2011-11-26 03:17:26 +00:00
kurtis.heimerl a14d4beb1a uhd: reset sample clock when time goes non-monotonic
With UHD b4fc0d61bb6cbd1a5614745bab9aeb0abc22cb6f

Sample clock will reset to zero after an overrun. Earlier
versions may hang the FPGA, which is non-recoverable,
requiring a manual image reload or reboot.

If reset to zero, attempt to kick the sample clock to the
last properly received timestamp value. At this point,
there will be a timing continuity jump, which will drop
connections, but transmit and receive chains should be
aligned allowing for re-establishment.

Signed-off-by: Thomas Tsou <ttsou@vt.edu>

git-svn-id: http://wush.net/svn/range/software/public/openbts/trunk@2645 19bc5d8c-e614-43d4-8b26-e1612bc8e597
2011-11-26 03:17:23 +00:00
kurtis.heimerl 24481decc2 uhd: move static functions into the uhd_device class
Simplifies things slightly, and this is supposed to be
C++ after all.

Signed-off-by: Thomas Tsou <ttsou@vt.edu>

git-svn-id: http://wush.net/svn/range/software/public/openbts/trunk@2643 19bc5d8c-e614-43d4-8b26-e1612bc8e597
2011-11-26 03:17:18 +00:00
kurtis.heimerl 02d04055a3 uhd: set and shadow settings through interface
Shadow all gains and frequencies, which minimizes device access.
This allows the transceiver to variably control the device
settings.

Signed-off-by: Thomas Tsou <ttsou@vt.edu>

git-svn-id: http://wush.net/svn/range/software/public/openbts/trunk@2640 19bc5d8c-e614-43d4-8b26-e1612bc8e597
2011-11-26 03:17:10 +00:00
kurtis.heimerl 993364485b uhd: set receive gain during initialization
This shouldn't matter much, but the gain settings through the
interface are short circuited right now, which makes this a
problem.

Signed-off-by: Thomas Tsou <ttsou@vt.edu>

git-svn-id: http://wush.net/svn/range/software/public/openbts/trunk@2639 19bc5d8c-e614-43d4-8b26-e1612bc8e597
2011-11-26 03:17:07 +00:00
kurtis.heimerl be6abe18cc uhd: set hardware side delay offset for e100
The value is used to align transmit and receive time slots within
a sample. This oscilloscope measured value is close, but may
need minor tweaking.

Signed-off-by: Thomas Tsou <ttsou@vt.edu>

git-svn-id: http://wush.net/svn/range/software/public/openbts/trunk@2638 19bc5d8c-e614-43d4-8b26-e1612bc8e597
2011-11-26 03:17:05 +00:00
kurtis.heimerl 3cc1da9d8b uhd: log useful information on monotonic errors
Track the current errant and previous timestamp values.

Signed-off-by: Thomas Tsou <ttsou@vt.edu>

git-svn-id: http://wush.net/svn/range/software/public/openbts/trunk@2637 19bc5d8c-e614-43d4-8b26-e1612bc8e597
2011-11-26 03:17:02 +00:00
kurtis.heimerl c491997c1e uhd: only the E100 supports FPGA timestamps and adjustable clock rate
Signed-off-by: Thomas Tsou <ttsou@vt.edu>

git-svn-id: http://wush.net/svn/range/software/public/openbts/trunk@2636 19bc5d8c-e614-43d4-8b26-e1612bc8e597
2011-11-26 03:17:00 +00:00
kurtis.heimerl 33f748f265 uhd: flush initial receive samples
Occasionally, the E100 will have errant timestamps at start
related to previous sessions. Early packets will be thrown
out anyways, so do this explicitly so the timestamps don't
royally fuck up the sample timing.

Signed-off-by: Thomas Tsou <ttsou@vt.edu>

git-svn-id: http://wush.net/svn/range/software/public/openbts/trunk@2635 19bc5d8c-e614-43d4-8b26-e1612bc8e597
2011-11-26 03:16:57 +00:00
kurtis.heimerl 965e757c53 uhd: add 52 MHz transceiver support
These are mostly identical changes as added to the non-52MHz
implementation with the exception of sample rate.

Signed-off-by: Thomas Tsou <ttsou@vt.edu>

git-svn-id: http://wush.net/svn/range/software/public/openbts/trunk@2634 19bc5d8c-e614-43d4-8b26-e1612bc8e597
2011-11-26 03:16:54 +00:00