Remove the paragraph about writing to the Free Software Foundation's
mailing address. The FSF has changed addresses in the past, and may do
so again. In 2021 this is not useful, let's rather have a bit less
boilerplate at the start of source files.
Change-Id: I8ba71ab9ccde4ba25151ecbeb2a323f706b57d43
Test files are moved from CommonLibs/ to tests/CommonLibs/.
Some tests are disabled in autotest because they generate timedate
related output which cannot exactly match against expected output.
Change-Id: I3d6ba625968be09297642d18090c496490e9b8fc
Implemeted with a Galois LFSR for speed and flexibility compared to Fibonacci version.
Aliases for three popular PRBS' are added for convenience - PRBS9, PRBS15 and PRBS64.
Note that we can't test PRBS64 completely, because the sequence is too long to
be generated.
Change-Id: Ib5331ba5d0b5819929541686fdd87905e2177b74
The ARM and the X86 implementation of the conversion functions share
the same, non cpu specific implementation in separate files.
This commit removes the code duplication by putting the generic
implementation into a convert_base.c, similar to to convolve_base.c
Change-Id: Ic8d8534a343e27cde79ddc85be4998ebd0cb6e5c
Complex-complex block multiples are used for phase rotation of
bursts. Optimization targeted from perf profiling.
Signed-off-by: Thomas Tsou <tom@tsou.cc>
Similar to the existing Intel SSE cases, add support for NEON vector
floating point SIMD processing. In this case, use ARM assembly
directly as the NEON intrinsics do not generate preferential code
output.
Currently support NEON vectorized convolution and floating point
integer conversions.
Signed-off-by: Thomas Tsou <tom@tsou.cc>
Oliver Smith
Pau Espin
Alexander Chemeris
Philipp Maier