Remove the paragraph about writing to the Free Software Foundation's
mailing address. The FSF has changed addresses in the past, and may do
so again. In 2021 this is not useful, let's rather have a bit less
boilerplate at the start of source files.
Change-Id: I8ba71ab9ccde4ba25151ecbeb2a323f706b57d43
- Those are not used any where
- Those are not supported by the sse/neon accelerated versions
- And I see very little use cases for those.
Change-Id: Ic850269a0ed5d98c0ea68980afd31016ed555b48
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
Take the chance to update some includes using files available in that
subdir to have them ina more uniform way.
Change-Id: Ibda3c54fd4dc3f6b845cc373f1a1e6b758c1ea82
Currently we find SSE3 and SSE4.1 code mixed togehter along with
generic code in one file. This introduces the risk that the
compiler exidantly mixes SSE4.1 instructions into an SSE3, or
even worse into a generic code path.
This commit splits the SSE3 and SSE4.1 code into separate files
and compiles them with the matching target options.
Change-Id: I846e190e92f1258cd412d1b2d79b539e204e04b3
The current implementation can select the SSE support level during
compiletime only.
This commit adds functionality to automatically detect and switch
the SSE support level and automatically switch the Implementation
if the CPU does not support the required SSE level.
Change-Id: Iba74f8a6e4e921ff31e4bd9f0c7c881fe547423a
The non-sse implementation and the sse implementation of the convert
and convolve functions have different parameter lists. This makes it
difficult to use function pointers in order to select the right
function depending on the SSE-Level and CPU.
This commit uniformizes the parameter lists in preparation for
planned runtime cpu detection support
Change-Id: Ice063b89791537c4b591751f12f5ef5c413a2d27
An errant shuffle register value used in complex-complex convolution
causes distorted correlation peak-to-average values for certain TSC
values. The error effect varies for different TSC sequences with the
most noticeable effect of degraded detection on TSC 1 and no effect on
TSC 7.
Signed-off-by: Thomas Tsou <tom@tsou.cc>
Move x86 specific files into their own directory as this
area is about to get crowded with the addition of ARM
support.
Signed-off-by: Thomas Tsou <tom@tsou.cc>
This large patch replaced the convolve() call with an SSE vector
enabled version. The lower C and SSE intrinsic based code operates
on fixed and aligned vectors for the filter taps. The storage format
of interleaved I/Q for both complex and real vectors is maintained.
SSE filter tap values must:
1. Start 16-byte aligned
2. Number with a multiple of 4 between 4 and 20 for real taps
3. Number with a multiple of 4 for complex taps
Non-compliant values will fall back to non-SSE usage. Fixed length
iterators mean that head and tail cases may require reallocation of
the input vector, which is automatically handled by the upper C++
interface.
Other calls are affected by these changes and adjusted or rewritten
accordingly. The underlying algorithms, however, are unchanged.
generateGSMPulse()
analyzeTrafficBurst()
detectRACHBurst()
Intel SSE configuration is automatically detected and configured at
build time with Autoconf macros.
Signed-off-by: Thomas Tsou <tom@tsou.cc>
Oliver Smith
Sylvain Munaut
Pau Espin
Philipp Maier
Tom Tsou