Remove the paragraph about writing to the Free Software Foundation's
mailing address. The FSF has changed addresses in the past, and may do
so again. In 2021 this is not useful, let's rather have a bit less
boilerplate at the start of source files.
Change-Id: I8ba71ab9ccde4ba25151ecbeb2a323f706b57d43
Take the chance to update some includes using files available in that
subdir to have them ina more uniform way.
Change-Id: Ibda3c54fd4dc3f6b845cc373f1a1e6b758c1ea82
Currently we find SSE3 and SSE4.1 code mixed togehter along with
generic code in one file. This introduces the risk that the
compiler exidantly mixes SSE4.1 instructions into an SSE3, or
even worse into a generic code path.
This commit splits the SSE3 and SSE4.1 code into separate files
and compiles them with the matching target options.
Change-Id: I846e190e92f1258cd412d1b2d79b539e204e04b3
The ARM and the X86 implementation of the conversion functions share
the same, non cpu specific implementation in separate files.
This commit removes the code duplication by putting the generic
implementation into a convert_base.c, similar to to convolve_base.c
Change-Id: Ic8d8534a343e27cde79ddc85be4998ebd0cb6e5c
Complex-complex block multiples are used for phase rotation of
bursts. Optimization targeted from perf profiling.
Signed-off-by: Thomas Tsou <tom@tsou.cc>
Similar to the existing Intel SSE cases, add support for NEON vector
floating point SIMD processing. In this case, use ARM assembly
directly as the NEON intrinsics do not generate preferential code
output.
Currently support NEON vectorized convolution and floating point
integer conversions.
Signed-off-by: Thomas Tsou <tom@tsou.cc>
Oliver Smith
Pau Espin
Philipp Maier
Thomas Tsou