Simplify helper function tbf_select_slot_set()
Store direction check to simplify the code. Get rid of 2-step LOGP to avoid multi-row logs in gsmtap log. Change-Id: Ia2e061da82ddce564b2d768d8ade1672c22934e2
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@ -711,7 +711,8 @@ static int tbf_select_slot_set(const gprs_rlcmac_tbf *tbf, const gprs_rlcmac_trx
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uint8_t reserved_ul_slots, uint8_t reserved_dl_slots,
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uint8_t reserved_ul_slots, uint8_t reserved_dl_slots,
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int8_t first_common_ts)
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int8_t first_common_ts)
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{
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{
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uint8_t sl = tbf->direction != GPRS_RLCMAC_DL_TBF ? ul_slots : dl_slots;
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bool is_ul = tbf->direction == GPRS_RLCMAC_UL_TBF;
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uint8_t sl = is_ul ? ul_slots : dl_slots;
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char slot_info[9] = { 0 };
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char slot_info[9] = { 0 };
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if (single)
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if (single)
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@ -719,22 +720,22 @@ static int tbf_select_slot_set(const gprs_rlcmac_tbf *tbf, const gprs_rlcmac_trx
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if (!sl) {
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if (!sl) {
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LOGP(DRLCMAC, LOGL_NOTICE, "No %s slots available\n",
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LOGP(DRLCMAC, LOGL_NOTICE, "No %s slots available\n",
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tbf->direction != GPRS_RLCMAC_DL_TBF ? "uplink" : "downlink");
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is_ul ? "uplink" : "downlink");
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bts_do_rate_ctr_inc(trx->bts, CTR_TBF_ALLOC_FAIL_NO_SLOT_AVAIL);
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bts_do_rate_ctr_inc(trx->bts, CTR_TBF_ALLOC_FAIL_NO_SLOT_AVAIL);
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return -EINVAL;
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return -EINVAL;
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}
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}
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if (tbf->direction != GPRS_RLCMAC_DL_TBF) {
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if (is_ul) {
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snprintf(slot_info, 9, OSMO_BIT_SPEC, OSMO_BIT_PRINT_EX(reserved_ul_slots, 'u'));
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snprintf(slot_info, 9, OSMO_BIT_SPEC, OSMO_BIT_PRINT_EX(reserved_ul_slots, 'u'));
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masked_override_with(slot_info, sl, 'U');
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masked_override_with(slot_info, sl, 'U');
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LOGP(DRLCMAC, LOGL_DEBUG, "- Selected UL");
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} else {
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} else {
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snprintf(slot_info, 9, OSMO_BIT_SPEC, OSMO_BIT_PRINT_EX(reserved_dl_slots, 'd'));
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snprintf(slot_info, 9, OSMO_BIT_SPEC, OSMO_BIT_PRINT_EX(reserved_dl_slots, 'd'));
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masked_override_with(slot_info, sl, 'D');
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masked_override_with(slot_info, sl, 'D');
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LOGP(DRLCMAC, LOGL_DEBUG, "- Selected DL");
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}
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}
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LOGPC(DRLCMAC, LOGL_DEBUG, " slots: (TS=0)\"%s\"(TS=7), %s\n", slot_info, single ? "single" : "multi");
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LOGPC(DRLCMAC, LOGL_DEBUG, "Selected %s slots: (TS=0)\"%s\"(TS=7), %s\n",
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is_ul ? "UL" : "DL",
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slot_info, single ? "single" : "multi");
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return sl;
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return sl;
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}
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}
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@ -3153,7 +3153,7 @@ Slot Allocation (Algorithm B) for class 12
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- Skipping TS 7, because not enabled
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- Skipping TS 7, because not enabled
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- Possible DL/UL slots: (TS=0)"..CCCC.."(TS=7)
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- Possible DL/UL slots: (TS=0)"..CCCC.."(TS=7)
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Rx=4 Tx=4 Sum Rx+Tx=5, Tta=2 Ttb=1, Tra=2 Trb=1, Type=1
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Rx=4 Tx=4 Sum Rx+Tx=5, Tta=2 Ttb=1, Tra=2 Trb=1, Type=1
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- Selected DL slots: (TS=0)"..DDDD.."(TS=7), multi
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Selected DL slots: (TS=0)"..DDDD.."(TS=7), multi
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[DL] algo B <multi> (suggested TRX: 0): using 4 slots
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[DL] algo B <multi> (suggested TRX: 0): using 4 slots
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- Reserved DL/UL slots: (TS=0)"..DDCD.."(TS=7)
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- Reserved DL/UL slots: (TS=0)"..DDCD.."(TS=7)
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- Assigning DL TS 2
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- Assigning DL TS 2
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@ -3192,7 +3192,7 @@ Slot Allocation (Algorithm B) for class 12
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- Skipping TS 7, because not enabled
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- Skipping TS 7, because not enabled
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- Possible DL/UL slots: (TS=0)"..CCCC.."(TS=7)
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- Possible DL/UL slots: (TS=0)"..CCCC.."(TS=7)
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Rx=4 Tx=4 Sum Rx+Tx=5, Tta=2 Ttb=1, Tra=2 Trb=1, Type=1
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Rx=4 Tx=4 Sum Rx+Tx=5, Tta=2 Ttb=1, Tra=2 Trb=1, Type=1
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- Selected DL slots: (TS=0)"..DDDD.."(TS=7), multi
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Selected DL slots: (TS=0)"..DDDD.."(TS=7), multi
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[DL] algo B <multi> (suggested TRX: 0): using 4 slots
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[DL] algo B <multi> (suggested TRX: 0): using 4 slots
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- Reserved DL/UL slots: (TS=0)"..DDCD.."(TS=7)
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- Reserved DL/UL slots: (TS=0)"..DDCD.."(TS=7)
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- Assigning DL TS 2
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- Assigning DL TS 2
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@ -6013,7 +6013,7 @@ Slot Allocation (Algorithm B) for class 11
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- Skipping TS 7, because not enabled
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- Skipping TS 7, because not enabled
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- Possible DL/UL slots: (TS=0)"..CCCC.."(TS=7)
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- Possible DL/UL slots: (TS=0)"..CCCC.."(TS=7)
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Rx=4 Tx=3 Sum Rx+Tx=5, Tta=3 Ttb=1, Tra=2 Trb=1, Type=1
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Rx=4 Tx=3 Sum Rx+Tx=5, Tta=3 Ttb=1, Tra=2 Trb=1, Type=1
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- Selected DL slots: (TS=0)"..ddDd.."(TS=7), single
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Selected DL slots: (TS=0)"..ddDd.."(TS=7), single
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[DL] algo B <single> (suggested TRX: 0): using single slot at TS 4
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[DL] algo B <single> (suggested TRX: 0): using single slot at TS 4
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- Reserved DL/UL slots: (TS=0)"...DC..."(TS=7)
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- Reserved DL/UL slots: (TS=0)"...DC..."(TS=7)
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- Assigning DL TS 4
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- Assigning DL TS 4
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@ -6028,7 +6028,7 @@ DL TBF slots: 0x10, N: 1, WS: 192
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PDCH(bts=0,trx=0,ts=4) Detaching TBF(TFI=0 TLLI=0xffffffff DIR=DL STATE=NULL EGPRS), 0 TBFs, USFs = 00, TFIs = 00000000.
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PDCH(bts=0,trx=0,ts=4) Detaching TBF(TFI=0 TLLI=0xffffffff DIR=DL STATE=NULL EGPRS), 0 TBFs, USFs = 00, TFIs = 00000000.
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[DL] algo B <multi> (suggested TRX: -1): Alloc start
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[DL] algo B <multi> (suggested TRX: -1): Alloc start
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Found first unallocated TRX=0 TFI=0
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Found first unallocated TRX=0 TFI=0
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- Selected DL slots: (TS=0)"..DDDD.."(TS=7), multi
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Selected DL slots: (TS=0)"..DDDD.."(TS=7), multi
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[DL] algo B <multi> (suggested TRX: -1): using 4 slots
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[DL] algo B <multi> (suggested TRX: -1): using 4 slots
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- Assigning DL TS 2
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- Assigning DL TS 2
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PDCH(bts=0,trx=0,ts=2) Attaching TBF(TFI=0 TLLI=0xffffffff DIR=DL STATE=NULL EGPRS), 1 TBFs, USFs = 00, TFIs = 00000001.
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PDCH(bts=0,trx=0,ts=2) Attaching TBF(TFI=0 TLLI=0xffffffff DIR=DL STATE=NULL EGPRS), 1 TBFs, USFs = 00, TFIs = 00000001.
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