1041 lines
71 KiB
C
1041 lines
71 KiB
C
/* Scheduler for OsmoBTS-TRX */
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/* (C) 2013 by Andreas Eversberg <jolly@eversberg.eu>
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* (C) 2015 by Alexander Chemeris <Alexander.Chemeris@fairwaves.co>
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* (C) 2015-2018 by Harald Welte <laforge@gnumonks.org>
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*
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU Affero General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU Affero General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#include <stdlib.h>
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#include <unistd.h>
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#include <errno.h>
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#include <stdint.h>
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#include <ctype.h>
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#include <osmocom/core/msgb.h>
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#include <osmocom/core/talloc.h>
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#include <osmo-bts/gsm_data.h>
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#include <osmo-bts/logging.h>
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#include <osmo-bts/scheduler.h>
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/*
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* multiframe structure
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*/
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static const struct trx_sched_frame frame_bcch[51] = {
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/* dl_chan dl_bid ul_chan ul_bid */
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{ TRXC_FCCH, 0, TRXC_RACH, 0 },
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{ TRXC_SCH, 0, TRXC_RACH, 0 },
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{ TRXC_BCCH, 0, TRXC_RACH, 0 }, { TRXC_BCCH, 1, TRXC_RACH, 0 }, { TRXC_BCCH, 2, TRXC_RACH, 0 }, { TRXC_BCCH, 3, TRXC_RACH, 0 },
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{ TRXC_CCCH, 0, TRXC_RACH, 0 }, { TRXC_CCCH, 1, TRXC_RACH, 0 }, { TRXC_CCCH, 2, TRXC_RACH, 0 }, { TRXC_CCCH, 3, TRXC_RACH, 0 },
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{ TRXC_FCCH, 0, TRXC_RACH, 0 },
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{ TRXC_SCH, 0, TRXC_RACH, 0 },
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{ TRXC_CCCH, 0, TRXC_RACH, 0 }, { TRXC_CCCH, 1, TRXC_RACH, 0 }, { TRXC_CCCH, 2, TRXC_RACH, 0 }, { TRXC_CCCH, 3, TRXC_RACH, 0 },
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{ TRXC_CCCH, 0, TRXC_RACH, 0 }, { TRXC_CCCH, 1, TRXC_RACH, 0 }, { TRXC_CCCH, 2, TRXC_RACH, 0 }, { TRXC_CCCH, 3, TRXC_RACH, 0 },
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{ TRXC_FCCH, 0, TRXC_RACH, 0 },
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{ TRXC_SCH, 0, TRXC_RACH, 0 },
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{ TRXC_CCCH, 0, TRXC_RACH, 0 }, { TRXC_CCCH, 1, TRXC_RACH, 0 }, { TRXC_CCCH, 2, TRXC_RACH, 0 }, { TRXC_CCCH, 3, TRXC_RACH, 0 },
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{ TRXC_CCCH, 0, TRXC_RACH, 0 }, { TRXC_CCCH, 1, TRXC_RACH, 0 }, { TRXC_CCCH, 2, TRXC_RACH, 0 }, { TRXC_CCCH, 3, TRXC_RACH, 0 },
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{ TRXC_FCCH, 0, TRXC_RACH, 0 },
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{ TRXC_SCH, 0, TRXC_RACH, 0 },
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{ TRXC_CCCH, 0, TRXC_RACH, 0 }, { TRXC_CCCH, 1, TRXC_RACH, 0 }, { TRXC_CCCH, 2, TRXC_RACH, 0 }, { TRXC_CCCH, 3, TRXC_RACH, 0 },
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{ TRXC_CCCH, 0, TRXC_RACH, 0 }, { TRXC_CCCH, 1, TRXC_RACH, 0 }, { TRXC_CCCH, 2, TRXC_RACH, 0 }, { TRXC_CCCH, 3, TRXC_RACH, 0 },
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{ TRXC_FCCH, 0, TRXC_RACH, 0 },
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{ TRXC_SCH, 0, TRXC_RACH, 0 },
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{ TRXC_CCCH, 0, TRXC_RACH, 0 }, { TRXC_CCCH, 1, TRXC_RACH, 0 }, { TRXC_CCCH, 2, TRXC_RACH, 0 }, { TRXC_CCCH, 3, TRXC_RACH, 0 },
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{ TRXC_CCCH, 0, TRXC_RACH, 0 }, { TRXC_CCCH, 1, TRXC_RACH, 0 }, { TRXC_CCCH, 2, TRXC_RACH, 0 }, { TRXC_CCCH, 3, TRXC_RACH, 0 },
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{ TRXC_IDLE, 0, TRXC_RACH, 0 },
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};
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static const struct trx_sched_frame frame_bcch_sdcch4[102] = {
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/* dl_chan dl_bid ul_chan ul_bid */
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{ TRXC_FCCH, 0, TRXC_SDCCH4_3, 0 },
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{ TRXC_SCH, 0, TRXC_SDCCH4_3, 1 },
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{ TRXC_BCCH, 0, TRXC_SDCCH4_3, 2 },
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{ TRXC_BCCH, 1, TRXC_SDCCH4_3, 3 },
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{ TRXC_BCCH, 2, TRXC_RACH, 0 },
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{ TRXC_BCCH, 3, TRXC_RACH, 0 },
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{ TRXC_CCCH, 0, TRXC_SACCH4_2, 0 },
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{ TRXC_CCCH, 1, TRXC_SACCH4_2, 1 },
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{ TRXC_CCCH, 2, TRXC_SACCH4_2, 2 },
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{ TRXC_CCCH, 3, TRXC_SACCH4_2, 3 },
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{ TRXC_FCCH, 0, TRXC_SACCH4_3, 0 },
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{ TRXC_SCH, 0, TRXC_SACCH4_3, 1 },
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{ TRXC_CCCH, 0, TRXC_SACCH4_3, 2 },
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{ TRXC_CCCH, 1, TRXC_SACCH4_3, 3 },
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{ TRXC_CCCH, 2, TRXC_RACH, 0 },
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{ TRXC_CCCH, 3, TRXC_RACH, 0 },
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{ TRXC_CCCH, 0, TRXC_RACH, 0 },
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{ TRXC_CCCH, 1, TRXC_RACH, 0 },
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{ TRXC_CCCH, 2, TRXC_RACH, 0 },
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{ TRXC_CCCH, 3, TRXC_RACH, 0 },
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{ TRXC_FCCH, 0, TRXC_RACH, 0 },
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{ TRXC_SCH, 0, TRXC_RACH, 0 },
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{ TRXC_SDCCH4_0, 0, TRXC_RACH, 0 },
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{ TRXC_SDCCH4_0, 1, TRXC_RACH, 0 },
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{ TRXC_SDCCH4_0, 2, TRXC_RACH, 0 },
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{ TRXC_SDCCH4_0, 3, TRXC_RACH, 0 },
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{ TRXC_SDCCH4_1, 0, TRXC_RACH, 0 },
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{ TRXC_SDCCH4_1, 1, TRXC_RACH, 0 },
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{ TRXC_SDCCH4_1, 2, TRXC_RACH, 0 },
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{ TRXC_SDCCH4_1, 3, TRXC_RACH, 0 },
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{ TRXC_FCCH, 0, TRXC_RACH, 0 },
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{ TRXC_SCH, 0, TRXC_RACH, 0 },
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{ TRXC_SDCCH4_2, 0, TRXC_RACH, 0 },
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{ TRXC_SDCCH4_2, 1, TRXC_RACH, 0 },
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{ TRXC_SDCCH4_2, 2, TRXC_RACH, 0 },
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{ TRXC_SDCCH4_2, 3, TRXC_RACH, 0 },
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{ TRXC_SDCCH4_3, 0, TRXC_RACH, 0 },
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{ TRXC_SDCCH4_3, 1, TRXC_SDCCH4_0, 0 },
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{ TRXC_SDCCH4_3, 2, TRXC_SDCCH4_0, 1 },
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{ TRXC_SDCCH4_3, 3, TRXC_SDCCH4_0, 2 },
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{ TRXC_FCCH, 0, TRXC_SDCCH4_0, 3 },
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{ TRXC_SCH, 0, TRXC_SDCCH4_1, 0 },
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{ TRXC_SACCH4_0, 0, TRXC_SDCCH4_1, 1 },
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{ TRXC_SACCH4_0, 1, TRXC_SDCCH4_1, 2 },
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{ TRXC_SACCH4_0, 2, TRXC_SDCCH4_1, 3 },
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{ TRXC_SACCH4_0, 3, TRXC_RACH, 0 },
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{ TRXC_SACCH4_1, 0, TRXC_RACH, 0 },
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{ TRXC_SACCH4_1, 1, TRXC_SDCCH4_2, 0 },
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{ TRXC_SACCH4_1, 2, TRXC_SDCCH4_2, 1 },
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{ TRXC_SACCH4_1, 3, TRXC_SDCCH4_2, 2 },
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{ TRXC_IDLE, 0, TRXC_SDCCH4_2, 3 },
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{ TRXC_FCCH, 0, TRXC_SDCCH4_3, 0 },
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{ TRXC_SCH, 0, TRXC_SDCCH4_3, 1 },
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{ TRXC_BCCH, 0, TRXC_SDCCH4_3, 2 },
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{ TRXC_BCCH, 1, TRXC_SDCCH4_3, 3 },
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{ TRXC_BCCH, 2, TRXC_RACH, 0 },
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{ TRXC_BCCH, 3, TRXC_RACH, 0 },
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{ TRXC_CCCH, 0, TRXC_SACCH4_0, 0 },
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{ TRXC_CCCH, 1, TRXC_SACCH4_0, 1 },
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{ TRXC_CCCH, 2, TRXC_SACCH4_0, 2 },
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{ TRXC_CCCH, 3, TRXC_SACCH4_0, 3 },
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{ TRXC_FCCH, 0, TRXC_SACCH4_1, 0 },
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{ TRXC_SCH, 0, TRXC_SACCH4_1, 1 },
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{ TRXC_CCCH, 0, TRXC_SACCH4_1, 2 },
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{ TRXC_CCCH, 1, TRXC_SACCH4_1, 3 },
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{ TRXC_CCCH, 2, TRXC_RACH, 0 },
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{ TRXC_CCCH, 3, TRXC_RACH, 0 },
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{ TRXC_CCCH, 0, TRXC_RACH, 0 },
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{ TRXC_CCCH, 1, TRXC_RACH, 0 },
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{ TRXC_CCCH, 2, TRXC_RACH, 0 },
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{ TRXC_CCCH, 3, TRXC_RACH, 0 },
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{ TRXC_FCCH, 0, TRXC_RACH, 0 },
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{ TRXC_SCH, 0, TRXC_RACH, 0 },
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{ TRXC_SDCCH4_0, 0, TRXC_RACH, 0 },
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{ TRXC_SDCCH4_0, 1, TRXC_RACH, 0 },
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{ TRXC_SDCCH4_0, 2, TRXC_RACH, 0 },
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{ TRXC_SDCCH4_0, 3, TRXC_RACH, 0 },
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{ TRXC_SDCCH4_1, 0, TRXC_RACH, 0 },
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{ TRXC_SDCCH4_1, 1, TRXC_RACH, 0 },
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{ TRXC_SDCCH4_1, 2, TRXC_RACH, 0 },
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{ TRXC_SDCCH4_1, 3, TRXC_RACH, 0 },
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{ TRXC_FCCH, 0, TRXC_RACH, 0 },
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{ TRXC_SCH, 0, TRXC_RACH, 0 },
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{ TRXC_SDCCH4_2, 0, TRXC_RACH, 0 },
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{ TRXC_SDCCH4_2, 1, TRXC_RACH, 0 },
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{ TRXC_SDCCH4_2, 2, TRXC_RACH, 0 },
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{ TRXC_SDCCH4_2, 3, TRXC_RACH, 0 },
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{ TRXC_SDCCH4_3, 0, TRXC_RACH, 0 },
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{ TRXC_SDCCH4_3, 1, TRXC_SDCCH4_0, 0 },
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{ TRXC_SDCCH4_3, 2, TRXC_SDCCH4_0, 1 },
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{ TRXC_SDCCH4_3, 3, TRXC_SDCCH4_0, 2 },
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{ TRXC_FCCH, 0, TRXC_SDCCH4_0, 3 },
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{ TRXC_SCH, 0, TRXC_SDCCH4_1, 0 },
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{ TRXC_SACCH4_2, 0, TRXC_SDCCH4_1, 1 },
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{ TRXC_SACCH4_2, 1, TRXC_SDCCH4_1, 2 },
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{ TRXC_SACCH4_2, 2, TRXC_SDCCH4_1, 3 },
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{ TRXC_SACCH4_2, 3, TRXC_RACH, 0 },
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{ TRXC_SACCH4_3, 0, TRXC_RACH, 0 },
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{ TRXC_SACCH4_3, 1, TRXC_SDCCH4_2, 0 },
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{ TRXC_SACCH4_3, 2, TRXC_SDCCH4_2, 1 },
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{ TRXC_SACCH4_3, 3, TRXC_SDCCH4_2, 2 },
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{ TRXC_IDLE, 0, TRXC_SDCCH4_2, 3 },
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};
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static const struct trx_sched_frame frame_bcch_sdcch4_cbch[102] = {
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/* dl_chan dl_bid ul_chan ul_bid */
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{ TRXC_FCCH, 0, TRXC_SDCCH4_3, 0 },
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{ TRXC_SCH, 0, TRXC_SDCCH4_3, 1 },
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{ TRXC_BCCH, 0, TRXC_SDCCH4_3, 2 },
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{ TRXC_BCCH, 1, TRXC_SDCCH4_3, 3 },
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{ TRXC_BCCH, 2, TRXC_RACH, 0 },
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{ TRXC_BCCH, 3, TRXC_RACH, 0 },
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{ TRXC_CCCH, 0, TRXC_IDLE, 0 },
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{ TRXC_CCCH, 1, TRXC_IDLE, 0 },
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{ TRXC_CCCH, 2, TRXC_IDLE, 0 },
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{ TRXC_CCCH, 3, TRXC_IDLE, 0 },
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{ TRXC_FCCH, 0, TRXC_SACCH4_3, 0 },
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{ TRXC_SCH, 0, TRXC_SACCH4_3, 1 },
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{ TRXC_CCCH, 0, TRXC_SACCH4_3, 2 },
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{ TRXC_CCCH, 1, TRXC_SACCH4_3, 3 },
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{ TRXC_CCCH, 2, TRXC_RACH, 0 },
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{ TRXC_CCCH, 3, TRXC_RACH, 0 },
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{ TRXC_CCCH, 0, TRXC_RACH, 0 },
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{ TRXC_CCCH, 1, TRXC_RACH, 0 },
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{ TRXC_CCCH, 2, TRXC_RACH, 0 },
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{ TRXC_CCCH, 3, TRXC_RACH, 0 },
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{ TRXC_FCCH, 0, TRXC_RACH, 0 },
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{ TRXC_SCH, 0, TRXC_RACH, 0 },
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{ TRXC_SDCCH4_0, 0, TRXC_RACH, 0 },
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{ TRXC_SDCCH4_0, 1, TRXC_RACH, 0 },
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{ TRXC_SDCCH4_0, 2, TRXC_RACH, 0 },
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{ TRXC_SDCCH4_0, 3, TRXC_RACH, 0 },
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{ TRXC_SDCCH4_1, 0, TRXC_RACH, 0 },
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{ TRXC_SDCCH4_1, 1, TRXC_RACH, 0 },
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{ TRXC_SDCCH4_1, 2, TRXC_RACH, 0 },
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{ TRXC_SDCCH4_1, 3, TRXC_RACH, 0 },
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{ TRXC_FCCH, 0, TRXC_RACH, 0 },
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{ TRXC_SCH, 0, TRXC_RACH, 0 },
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{ TRXC_CBCH, 0, TRXC_RACH, 0 },
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{ TRXC_CBCH, 1, TRXC_RACH, 0 },
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{ TRXC_CBCH, 2, TRXC_RACH, 0 },
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{ TRXC_CBCH, 3, TRXC_RACH, 0 },
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{ TRXC_SDCCH4_3, 0, TRXC_RACH, 0 },
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{ TRXC_SDCCH4_3, 1, TRXC_SDCCH4_0, 0 },
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{ TRXC_SDCCH4_3, 2, TRXC_SDCCH4_0, 1 },
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{ TRXC_SDCCH4_3, 3, TRXC_SDCCH4_0, 2 },
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{ TRXC_FCCH, 0, TRXC_SDCCH4_0, 3 },
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{ TRXC_SCH, 0, TRXC_SDCCH4_1, 0 },
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{ TRXC_SACCH4_0, 0, TRXC_SDCCH4_1, 1 },
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{ TRXC_SACCH4_0, 1, TRXC_SDCCH4_1, 2 },
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{ TRXC_SACCH4_0, 2, TRXC_SDCCH4_1, 3 },
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{ TRXC_SACCH4_0, 3, TRXC_RACH, 0 },
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{ TRXC_SACCH4_1, 0, TRXC_RACH, 0 },
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{ TRXC_SACCH4_1, 1, TRXC_IDLE, 0 },
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{ TRXC_SACCH4_1, 2, TRXC_IDLE, 0 },
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{ TRXC_SACCH4_1, 3, TRXC_IDLE, 0 },
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{ TRXC_IDLE, 0, TRXC_IDLE, 0 },
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{ TRXC_FCCH, 0, TRXC_SDCCH4_3, 0 },
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{ TRXC_SCH, 0, TRXC_SDCCH4_3, 1 },
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{ TRXC_BCCH, 0, TRXC_SDCCH4_3, 2 },
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{ TRXC_BCCH, 1, TRXC_SDCCH4_3, 3 },
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{ TRXC_BCCH, 2, TRXC_RACH, 0 },
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{ TRXC_BCCH, 3, TRXC_RACH, 0 },
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{ TRXC_CCCH, 0, TRXC_SACCH4_0, 0 },
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{ TRXC_CCCH, 1, TRXC_SACCH4_0, 1 },
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{ TRXC_CCCH, 2, TRXC_SACCH4_0, 2 },
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{ TRXC_CCCH, 3, TRXC_SACCH4_0, 3 },
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{ TRXC_FCCH, 0, TRXC_SACCH4_1, 0 },
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{ TRXC_SCH, 0, TRXC_SACCH4_1, 1 },
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{ TRXC_CCCH, 0, TRXC_SACCH4_1, 2 },
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{ TRXC_CCCH, 1, TRXC_SACCH4_1, 3 },
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{ TRXC_CCCH, 2, TRXC_RACH, 0 },
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{ TRXC_CCCH, 3, TRXC_RACH, 0 },
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{ TRXC_CCCH, 0, TRXC_RACH, 0 },
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{ TRXC_CCCH, 1, TRXC_RACH, 0 },
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{ TRXC_CCCH, 2, TRXC_RACH, 0 },
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{ TRXC_CCCH, 3, TRXC_RACH, 0 },
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{ TRXC_FCCH, 0, TRXC_RACH, 0 },
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{ TRXC_SCH, 0, TRXC_RACH, 0 },
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{ TRXC_SDCCH4_0, 0, TRXC_RACH, 0 },
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{ TRXC_SDCCH4_0, 1, TRXC_RACH, 0 },
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{ TRXC_SDCCH4_0, 2, TRXC_RACH, 0 },
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{ TRXC_SDCCH4_0, 3, TRXC_RACH, 0 },
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{ TRXC_SDCCH4_1, 0, TRXC_RACH, 0 },
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{ TRXC_SDCCH4_1, 1, TRXC_RACH, 0 },
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{ TRXC_SDCCH4_1, 2, TRXC_RACH, 0 },
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{ TRXC_SDCCH4_1, 3, TRXC_RACH, 0 },
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{ TRXC_FCCH, 0, TRXC_RACH, 0 },
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{ TRXC_SCH, 0, TRXC_RACH, 0 },
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{ TRXC_CBCH, 0, TRXC_RACH, 0 },
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{ TRXC_CBCH, 1, TRXC_RACH, 0 },
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{ TRXC_CBCH, 2, TRXC_RACH, 0 },
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{ TRXC_CBCH, 3, TRXC_RACH, 0 },
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{ TRXC_SDCCH4_3, 0, TRXC_RACH, 0 },
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{ TRXC_SDCCH4_3, 1, TRXC_SDCCH4_0, 0 },
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{ TRXC_SDCCH4_3, 2, TRXC_SDCCH4_0, 1 },
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{ TRXC_SDCCH4_3, 3, TRXC_SDCCH4_0, 2 },
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{ TRXC_FCCH, 0, TRXC_SDCCH4_0, 3 },
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{ TRXC_SCH, 0, TRXC_SDCCH4_1, 0 },
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{ TRXC_IDLE, 0, TRXC_SDCCH4_1, 1 },
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{ TRXC_IDLE, 0, TRXC_SDCCH4_1, 2 },
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{ TRXC_IDLE, 0, TRXC_SDCCH4_1, 3 },
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{ TRXC_IDLE, 0, TRXC_RACH, 0 },
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{ TRXC_SACCH4_3, 0, TRXC_RACH, 0 },
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{ TRXC_SACCH4_3, 1, TRXC_IDLE, 0 },
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{ TRXC_SACCH4_3, 2, TRXC_IDLE, 0 },
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{ TRXC_SACCH4_3, 3, TRXC_IDLE, 0 },
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{ TRXC_IDLE, 0, TRXC_IDLE, 0 },
|
|
};
|
|
|
|
static const struct trx_sched_frame frame_sdcch8[102] = {
|
|
/* dl_chan dl_bid ul_chan ul_bid */
|
|
{ TRXC_SDCCH8_0, 0, TRXC_SACCH8_5, 0 },
|
|
{ TRXC_SDCCH8_0, 1, TRXC_SACCH8_5, 1 },
|
|
{ TRXC_SDCCH8_0, 2, TRXC_SACCH8_5, 2 },
|
|
{ TRXC_SDCCH8_0, 3, TRXC_SACCH8_5, 3 },
|
|
{ TRXC_SDCCH8_1, 0, TRXC_SACCH8_6, 0 },
|
|
{ TRXC_SDCCH8_1, 1, TRXC_SACCH8_6, 1 },
|
|
{ TRXC_SDCCH8_1, 2, TRXC_SACCH8_6, 2 },
|
|
{ TRXC_SDCCH8_1, 3, TRXC_SACCH8_6, 3 },
|
|
{ TRXC_SDCCH8_2, 0, TRXC_SACCH8_7, 0 },
|
|
{ TRXC_SDCCH8_2, 1, TRXC_SACCH8_7, 1 },
|
|
{ TRXC_SDCCH8_2, 2, TRXC_SACCH8_7, 2 },
|
|
{ TRXC_SDCCH8_2, 3, TRXC_SACCH8_7, 3 },
|
|
{ TRXC_SDCCH8_3, 0, TRXC_IDLE, 0 },
|
|
{ TRXC_SDCCH8_3, 1, TRXC_IDLE, 0 },
|
|
{ TRXC_SDCCH8_3, 2, TRXC_IDLE, 0 },
|
|
{ TRXC_SDCCH8_3, 3, TRXC_SDCCH8_0, 0 },
|
|
{ TRXC_SDCCH8_4, 0, TRXC_SDCCH8_0, 1 },
|
|
{ TRXC_SDCCH8_4, 1, TRXC_SDCCH8_0, 2 },
|
|
{ TRXC_SDCCH8_4, 2, TRXC_SDCCH8_0, 3 },
|
|
{ TRXC_SDCCH8_4, 3, TRXC_SDCCH8_1, 0 },
|
|
{ TRXC_SDCCH8_5, 0, TRXC_SDCCH8_1, 1 },
|
|
{ TRXC_SDCCH8_5, 1, TRXC_SDCCH8_1, 2 },
|
|
{ TRXC_SDCCH8_5, 2, TRXC_SDCCH8_1, 3 },
|
|
{ TRXC_SDCCH8_5, 3, TRXC_SDCCH8_2, 0 },
|
|
{ TRXC_SDCCH8_6, 0, TRXC_SDCCH8_2, 1 },
|
|
{ TRXC_SDCCH8_6, 1, TRXC_SDCCH8_2, 2 },
|
|
{ TRXC_SDCCH8_6, 2, TRXC_SDCCH8_2, 3 },
|
|
{ TRXC_SDCCH8_6, 3, TRXC_SDCCH8_3, 0 },
|
|
{ TRXC_SDCCH8_7, 0, TRXC_SDCCH8_3, 1 },
|
|
{ TRXC_SDCCH8_7, 1, TRXC_SDCCH8_3, 2 },
|
|
{ TRXC_SDCCH8_7, 2, TRXC_SDCCH8_3, 3 },
|
|
{ TRXC_SDCCH8_7, 3, TRXC_SDCCH8_4, 0 },
|
|
{ TRXC_SACCH8_0, 0, TRXC_SDCCH8_4, 1 },
|
|
{ TRXC_SACCH8_0, 1, TRXC_SDCCH8_4, 2 },
|
|
{ TRXC_SACCH8_0, 2, TRXC_SDCCH8_4, 3 },
|
|
{ TRXC_SACCH8_0, 3, TRXC_SDCCH8_5, 0 },
|
|
{ TRXC_SACCH8_1, 0, TRXC_SDCCH8_5, 1 },
|
|
{ TRXC_SACCH8_1, 1, TRXC_SDCCH8_5, 2 },
|
|
{ TRXC_SACCH8_1, 2, TRXC_SDCCH8_5, 3 },
|
|
{ TRXC_SACCH8_1, 3, TRXC_SDCCH8_6, 0 },
|
|
{ TRXC_SACCH8_2, 0, TRXC_SDCCH8_6, 1 },
|
|
{ TRXC_SACCH8_2, 1, TRXC_SDCCH8_6, 2 },
|
|
{ TRXC_SACCH8_2, 2, TRXC_SDCCH8_6, 3 },
|
|
{ TRXC_SACCH8_2, 3, TRXC_SDCCH8_7, 0 },
|
|
{ TRXC_SACCH8_3, 0, TRXC_SDCCH8_7, 1 },
|
|
{ TRXC_SACCH8_3, 1, TRXC_SDCCH8_7, 2 },
|
|
{ TRXC_SACCH8_3, 2, TRXC_SDCCH8_7, 3 },
|
|
{ TRXC_SACCH8_3, 3, TRXC_SACCH8_0, 0 },
|
|
{ TRXC_IDLE, 0, TRXC_SACCH8_0, 1 },
|
|
{ TRXC_IDLE, 0, TRXC_SACCH8_0, 2 },
|
|
{ TRXC_IDLE, 0, TRXC_SACCH8_0, 3 },
|
|
|
|
{ TRXC_SDCCH8_0, 0, TRXC_SACCH8_1, 0 },
|
|
{ TRXC_SDCCH8_0, 1, TRXC_SACCH8_1, 1 },
|
|
{ TRXC_SDCCH8_0, 2, TRXC_SACCH8_1, 2 },
|
|
{ TRXC_SDCCH8_0, 3, TRXC_SACCH8_1, 3 },
|
|
{ TRXC_SDCCH8_1, 0, TRXC_SACCH8_2, 0 },
|
|
{ TRXC_SDCCH8_1, 1, TRXC_SACCH8_2, 1 },
|
|
{ TRXC_SDCCH8_1, 2, TRXC_SACCH8_2, 2 },
|
|
{ TRXC_SDCCH8_1, 3, TRXC_SACCH8_2, 3 },
|
|
{ TRXC_SDCCH8_2, 0, TRXC_SACCH8_3, 0 },
|
|
{ TRXC_SDCCH8_2, 1, TRXC_SACCH8_3, 1 },
|
|
{ TRXC_SDCCH8_2, 2, TRXC_SACCH8_3, 2 },
|
|
{ TRXC_SDCCH8_2, 3, TRXC_SACCH8_3, 3 },
|
|
{ TRXC_SDCCH8_3, 0, TRXC_IDLE, 0 },
|
|
{ TRXC_SDCCH8_3, 1, TRXC_IDLE, 0 },
|
|
{ TRXC_SDCCH8_3, 2, TRXC_IDLE, 0 },
|
|
{ TRXC_SDCCH8_3, 3, TRXC_SDCCH8_0, 0 },
|
|
{ TRXC_SDCCH8_4, 0, TRXC_SDCCH8_0, 1 },
|
|
{ TRXC_SDCCH8_4, 1, TRXC_SDCCH8_0, 2 },
|
|
{ TRXC_SDCCH8_4, 2, TRXC_SDCCH8_0, 3 },
|
|
{ TRXC_SDCCH8_4, 3, TRXC_SDCCH8_1, 0 },
|
|
{ TRXC_SDCCH8_5, 0, TRXC_SDCCH8_1, 1 },
|
|
{ TRXC_SDCCH8_5, 1, TRXC_SDCCH8_1, 2 },
|
|
{ TRXC_SDCCH8_5, 2, TRXC_SDCCH8_1, 3 },
|
|
{ TRXC_SDCCH8_5, 3, TRXC_SDCCH8_2, 0 },
|
|
{ TRXC_SDCCH8_6, 0, TRXC_SDCCH8_2, 1 },
|
|
{ TRXC_SDCCH8_6, 1, TRXC_SDCCH8_2, 2 },
|
|
{ TRXC_SDCCH8_6, 2, TRXC_SDCCH8_2, 3 },
|
|
{ TRXC_SDCCH8_6, 3, TRXC_SDCCH8_3, 0 },
|
|
{ TRXC_SDCCH8_7, 0, TRXC_SDCCH8_3, 1 },
|
|
{ TRXC_SDCCH8_7, 1, TRXC_SDCCH8_3, 2 },
|
|
{ TRXC_SDCCH8_7, 2, TRXC_SDCCH8_3, 3 },
|
|
{ TRXC_SDCCH8_7, 3, TRXC_SDCCH8_4, 0 },
|
|
{ TRXC_SACCH8_4, 0, TRXC_SDCCH8_4, 1 },
|
|
{ TRXC_SACCH8_4, 1, TRXC_SDCCH8_4, 2 },
|
|
{ TRXC_SACCH8_4, 2, TRXC_SDCCH8_4, 3 },
|
|
{ TRXC_SACCH8_4, 3, TRXC_SDCCH8_5, 0 },
|
|
{ TRXC_SACCH8_5, 0, TRXC_SDCCH8_5, 1 },
|
|
{ TRXC_SACCH8_5, 1, TRXC_SDCCH8_5, 2 },
|
|
{ TRXC_SACCH8_5, 2, TRXC_SDCCH8_5, 3 },
|
|
{ TRXC_SACCH8_5, 3, TRXC_SDCCH8_6, 0 },
|
|
{ TRXC_SACCH8_6, 0, TRXC_SDCCH8_6, 1 },
|
|
{ TRXC_SACCH8_6, 1, TRXC_SDCCH8_6, 2 },
|
|
{ TRXC_SACCH8_6, 2, TRXC_SDCCH8_6, 3 },
|
|
{ TRXC_SACCH8_6, 3, TRXC_SDCCH8_7, 0 },
|
|
{ TRXC_SACCH8_7, 0, TRXC_SDCCH8_7, 1 },
|
|
{ TRXC_SACCH8_7, 1, TRXC_SDCCH8_7, 2 },
|
|
{ TRXC_SACCH8_7, 2, TRXC_SDCCH8_7, 3 },
|
|
{ TRXC_SACCH8_7, 3, TRXC_SACCH8_4, 0 },
|
|
{ TRXC_IDLE, 0, TRXC_SACCH8_4, 1 },
|
|
{ TRXC_IDLE, 0, TRXC_SACCH8_4, 2 },
|
|
{ TRXC_IDLE, 0, TRXC_SACCH8_4, 3 },
|
|
};
|
|
|
|
static const struct trx_sched_frame frame_sdcch8_cbch[102] = {
|
|
/* dl_chan dl_bid ul_chan ul_bid */
|
|
{ TRXC_SDCCH8_0, 0, TRXC_SACCH8_5, 0 },
|
|
{ TRXC_SDCCH8_0, 1, TRXC_SACCH8_5, 1 },
|
|
{ TRXC_SDCCH8_0, 2, TRXC_SACCH8_5, 2 },
|
|
{ TRXC_SDCCH8_0, 3, TRXC_SACCH8_5, 3 },
|
|
{ TRXC_SDCCH8_1, 0, TRXC_SACCH8_6, 0 },
|
|
{ TRXC_SDCCH8_1, 1, TRXC_SACCH8_6, 1 },
|
|
{ TRXC_SDCCH8_1, 2, TRXC_SACCH8_6, 2 },
|
|
{ TRXC_SDCCH8_1, 3, TRXC_SACCH8_6, 3 },
|
|
{ TRXC_CBCH, 0, TRXC_SACCH8_7, 0 },
|
|
{ TRXC_CBCH, 1, TRXC_SACCH8_7, 1 },
|
|
{ TRXC_CBCH, 2, TRXC_SACCH8_7, 2 },
|
|
{ TRXC_CBCH, 3, TRXC_SACCH8_7, 3 },
|
|
{ TRXC_SDCCH8_3, 0, TRXC_IDLE, 0 },
|
|
{ TRXC_SDCCH8_3, 1, TRXC_IDLE, 0 },
|
|
{ TRXC_SDCCH8_3, 2, TRXC_IDLE, 0 },
|
|
{ TRXC_SDCCH8_3, 3, TRXC_SDCCH8_0, 0 },
|
|
{ TRXC_SDCCH8_4, 0, TRXC_SDCCH8_0, 1 },
|
|
{ TRXC_SDCCH8_4, 1, TRXC_SDCCH8_0, 2 },
|
|
{ TRXC_SDCCH8_4, 2, TRXC_SDCCH8_0, 3 },
|
|
{ TRXC_SDCCH8_4, 3, TRXC_SDCCH8_1, 0 },
|
|
{ TRXC_SDCCH8_5, 0, TRXC_SDCCH8_1, 1 },
|
|
{ TRXC_SDCCH8_5, 1, TRXC_SDCCH8_1, 2 },
|
|
{ TRXC_SDCCH8_5, 2, TRXC_SDCCH8_1, 3 },
|
|
{ TRXC_SDCCH8_5, 3, TRXC_IDLE, 0 },
|
|
{ TRXC_SDCCH8_6, 0, TRXC_IDLE, 1 },
|
|
{ TRXC_SDCCH8_6, 1, TRXC_IDLE, 2 },
|
|
{ TRXC_SDCCH8_6, 2, TRXC_IDLE, 3 },
|
|
{ TRXC_SDCCH8_6, 3, TRXC_SDCCH8_3, 0 },
|
|
{ TRXC_SDCCH8_7, 0, TRXC_SDCCH8_3, 1 },
|
|
{ TRXC_SDCCH8_7, 1, TRXC_SDCCH8_3, 2 },
|
|
{ TRXC_SDCCH8_7, 2, TRXC_SDCCH8_3, 3 },
|
|
{ TRXC_SDCCH8_7, 3, TRXC_SDCCH8_4, 0 },
|
|
{ TRXC_SACCH8_0, 0, TRXC_SDCCH8_4, 1 },
|
|
{ TRXC_SACCH8_0, 1, TRXC_SDCCH8_4, 2 },
|
|
{ TRXC_SACCH8_0, 2, TRXC_SDCCH8_4, 3 },
|
|
{ TRXC_SACCH8_0, 3, TRXC_SDCCH8_5, 0 },
|
|
{ TRXC_SACCH8_1, 0, TRXC_SDCCH8_5, 1 },
|
|
{ TRXC_SACCH8_1, 1, TRXC_SDCCH8_5, 2 },
|
|
{ TRXC_SACCH8_1, 2, TRXC_SDCCH8_5, 3 },
|
|
{ TRXC_SACCH8_1, 3, TRXC_SDCCH8_6, 0 },
|
|
{ TRXC_IDLE, 0, TRXC_SDCCH8_6, 1 },
|
|
{ TRXC_IDLE, 1, TRXC_SDCCH8_6, 2 },
|
|
{ TRXC_IDLE, 2, TRXC_SDCCH8_6, 3 },
|
|
{ TRXC_IDLE, 3, TRXC_SDCCH8_7, 0 },
|
|
{ TRXC_SACCH8_3, 0, TRXC_SDCCH8_7, 1 },
|
|
{ TRXC_SACCH8_3, 1, TRXC_SDCCH8_7, 2 },
|
|
{ TRXC_SACCH8_3, 2, TRXC_SDCCH8_7, 3 },
|
|
{ TRXC_SACCH8_3, 3, TRXC_SACCH8_0, 0 },
|
|
{ TRXC_IDLE, 0, TRXC_SACCH8_0, 1 },
|
|
{ TRXC_IDLE, 0, TRXC_SACCH8_0, 2 },
|
|
{ TRXC_IDLE, 0, TRXC_SACCH8_0, 3 },
|
|
|
|
{ TRXC_SDCCH8_0, 0, TRXC_SACCH8_1, 0 },
|
|
{ TRXC_SDCCH8_0, 1, TRXC_SACCH8_1, 1 },
|
|
{ TRXC_SDCCH8_0, 2, TRXC_SACCH8_1, 2 },
|
|
{ TRXC_SDCCH8_0, 3, TRXC_SACCH8_1, 3 },
|
|
{ TRXC_SDCCH8_1, 0, TRXC_IDLE, 0 },
|
|
{ TRXC_SDCCH8_1, 1, TRXC_IDLE, 1 },
|
|
{ TRXC_SDCCH8_1, 2, TRXC_IDLE, 2 },
|
|
{ TRXC_SDCCH8_1, 3, TRXC_IDLE, 3 },
|
|
{ TRXC_CBCH, 0, TRXC_SACCH8_3, 0 },
|
|
{ TRXC_CBCH, 1, TRXC_SACCH8_3, 1 },
|
|
{ TRXC_CBCH, 2, TRXC_SACCH8_3, 2 },
|
|
{ TRXC_CBCH, 3, TRXC_SACCH8_3, 3 },
|
|
{ TRXC_SDCCH8_3, 0, TRXC_IDLE, 0 },
|
|
{ TRXC_SDCCH8_3, 1, TRXC_IDLE, 0 },
|
|
{ TRXC_SDCCH8_3, 2, TRXC_IDLE, 0 },
|
|
{ TRXC_SDCCH8_3, 3, TRXC_SDCCH8_0, 0 },
|
|
{ TRXC_SDCCH8_4, 0, TRXC_SDCCH8_0, 1 },
|
|
{ TRXC_SDCCH8_4, 1, TRXC_SDCCH8_0, 2 },
|
|
{ TRXC_SDCCH8_4, 2, TRXC_SDCCH8_0, 3 },
|
|
{ TRXC_SDCCH8_4, 3, TRXC_SDCCH8_1, 0 },
|
|
{ TRXC_SDCCH8_5, 0, TRXC_SDCCH8_1, 1 },
|
|
{ TRXC_SDCCH8_5, 1, TRXC_SDCCH8_1, 2 },
|
|
{ TRXC_SDCCH8_5, 2, TRXC_SDCCH8_1, 3 },
|
|
{ TRXC_SDCCH8_5, 3, TRXC_IDLE, 0 },
|
|
{ TRXC_SDCCH8_6, 0, TRXC_IDLE, 1 },
|
|
{ TRXC_SDCCH8_6, 1, TRXC_IDLE, 2 },
|
|
{ TRXC_SDCCH8_6, 2, TRXC_IDLE, 3 },
|
|
{ TRXC_SDCCH8_6, 3, TRXC_SDCCH8_3, 0 },
|
|
{ TRXC_SDCCH8_7, 0, TRXC_SDCCH8_3, 1 },
|
|
{ TRXC_SDCCH8_7, 1, TRXC_SDCCH8_3, 2 },
|
|
{ TRXC_SDCCH8_7, 2, TRXC_SDCCH8_3, 3 },
|
|
{ TRXC_SDCCH8_7, 3, TRXC_SDCCH8_4, 0 },
|
|
{ TRXC_SACCH8_4, 0, TRXC_SDCCH8_4, 1 },
|
|
{ TRXC_SACCH8_4, 1, TRXC_SDCCH8_4, 2 },
|
|
{ TRXC_SACCH8_4, 2, TRXC_SDCCH8_4, 3 },
|
|
{ TRXC_SACCH8_4, 3, TRXC_SDCCH8_5, 0 },
|
|
{ TRXC_SACCH8_5, 0, TRXC_SDCCH8_5, 1 },
|
|
{ TRXC_SACCH8_5, 1, TRXC_SDCCH8_5, 2 },
|
|
{ TRXC_SACCH8_5, 2, TRXC_SDCCH8_5, 3 },
|
|
{ TRXC_SACCH8_5, 3, TRXC_SDCCH8_6, 0 },
|
|
{ TRXC_SACCH8_6, 0, TRXC_SDCCH8_6, 1 },
|
|
{ TRXC_SACCH8_6, 1, TRXC_SDCCH8_6, 2 },
|
|
{ TRXC_SACCH8_6, 2, TRXC_SDCCH8_6, 3 },
|
|
{ TRXC_SACCH8_6, 3, TRXC_SDCCH8_7, 0 },
|
|
{ TRXC_SACCH8_7, 0, TRXC_SDCCH8_7, 1 },
|
|
{ TRXC_SACCH8_7, 1, TRXC_SDCCH8_7, 2 },
|
|
{ TRXC_SACCH8_7, 2, TRXC_SDCCH8_7, 3 },
|
|
{ TRXC_SACCH8_7, 3, TRXC_SACCH8_4, 0 },
|
|
{ TRXC_IDLE, 0, TRXC_SACCH8_4, 1 },
|
|
{ TRXC_IDLE, 0, TRXC_SACCH8_4, 2 },
|
|
{ TRXC_IDLE, 0, TRXC_SACCH8_4, 3 },
|
|
};
|
|
|
|
static const struct trx_sched_frame frame_tchf_ts0[104] = {
|
|
/* dl_chan dl_bid ul_chan ul_bid */
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_SACCHTF, 0, TRXC_SACCHTF, 0 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_IDLE, 0, TRXC_IDLE, 0 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_SACCHTF, 1, TRXC_SACCHTF, 1 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_IDLE, 0, TRXC_IDLE, 0 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_SACCHTF, 2, TRXC_SACCHTF, 2 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_IDLE, 0, TRXC_IDLE, 0 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_SACCHTF, 3, TRXC_SACCHTF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_IDLE, 0, TRXC_IDLE, 0 },
|
|
};
|
|
|
|
static const struct trx_sched_frame frame_tchf_ts1[104] = {
|
|
/* dl_chan dl_bid ul_chan ul_bid */
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_IDLE, 0, TRXC_IDLE, 0 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_SACCHTF, 0, TRXC_SACCHTF, 0 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_IDLE, 0, TRXC_IDLE, 0 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_SACCHTF, 1, TRXC_SACCHTF, 1 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_IDLE, 0, TRXC_IDLE, 0 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_SACCHTF, 2, TRXC_SACCHTF, 2 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_IDLE, 0, TRXC_IDLE, 0 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_SACCHTF, 3, TRXC_SACCHTF, 3 },
|
|
};
|
|
|
|
static const struct trx_sched_frame frame_tchf_ts2[104] = {
|
|
/* dl_chan dl_bid ul_chan ul_bid */
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_SACCHTF, 3, TRXC_SACCHTF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_IDLE, 0, TRXC_IDLE, 0 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_SACCHTF, 0, TRXC_SACCHTF, 0 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_IDLE, 0, TRXC_IDLE, 0 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_SACCHTF, 1, TRXC_SACCHTF, 1 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_IDLE, 0, TRXC_IDLE, 0 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_SACCHTF, 2, TRXC_SACCHTF, 2 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_IDLE, 0, TRXC_IDLE, 0 },
|
|
};
|
|
|
|
static const struct trx_sched_frame frame_tchf_ts3[104] = {
|
|
/* dl_chan dl_bid ul_chan ul_bid */
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_IDLE, 0, TRXC_IDLE, 0 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_SACCHTF, 3, TRXC_SACCHTF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_IDLE, 0, TRXC_IDLE, 0 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_SACCHTF, 0, TRXC_SACCHTF, 0 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_IDLE, 0, TRXC_IDLE, 0 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_SACCHTF, 1, TRXC_SACCHTF, 1 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_IDLE, 0, TRXC_IDLE, 0 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_SACCHTF, 2, TRXC_SACCHTF, 2 },
|
|
};
|
|
|
|
static const struct trx_sched_frame frame_tchf_ts4[104] = {
|
|
/* dl_chan dl_bid ul_chan ul_bid */
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_SACCHTF, 2, TRXC_SACCHTF, 2 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_IDLE, 0, TRXC_IDLE, 0 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_SACCHTF, 3, TRXC_SACCHTF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_IDLE, 0, TRXC_IDLE, 0 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_SACCHTF, 0, TRXC_SACCHTF, 0 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_IDLE, 0, TRXC_IDLE, 0 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_SACCHTF, 1, TRXC_SACCHTF, 1 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_IDLE, 0, TRXC_IDLE, 0 },
|
|
};
|
|
|
|
static const struct trx_sched_frame frame_tchf_ts5[104] = {
|
|
/* dl_chan dl_bid ul_chan ul_bid */
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_IDLE, 0, TRXC_IDLE, 0 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_SACCHTF, 2, TRXC_SACCHTF, 2 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_IDLE, 0, TRXC_IDLE, 0 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_SACCHTF, 3, TRXC_SACCHTF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_IDLE, 0, TRXC_IDLE, 0 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_SACCHTF, 0, TRXC_SACCHTF, 0 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_IDLE, 0, TRXC_IDLE, 0 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_SACCHTF, 1, TRXC_SACCHTF, 1 },
|
|
};
|
|
|
|
static const struct trx_sched_frame frame_tchf_ts6[104] = {
|
|
/* dl_chan dl_bid ul_chan ul_bid */
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_SACCHTF, 1, TRXC_SACCHTF, 1 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_IDLE, 0, TRXC_IDLE, 0 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_SACCHTF, 2, TRXC_SACCHTF, 2 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_IDLE, 0, TRXC_IDLE, 0 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_SACCHTF, 3, TRXC_SACCHTF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_IDLE, 0, TRXC_IDLE, 0 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_SACCHTF, 0, TRXC_SACCHTF, 0 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
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|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
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|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_IDLE, 0, TRXC_IDLE, 0 },
|
|
};
|
|
|
|
static const struct trx_sched_frame frame_tchf_ts7[104] = {
|
|
/* dl_chan dl_bid ul_chan ul_bid */
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|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
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|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
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|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
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{ TRXC_IDLE, 0, TRXC_IDLE, 0 },
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|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
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{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
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|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
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{ TRXC_SACCHTF, 1, TRXC_SACCHTF, 1 },
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|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
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|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
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{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
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{ TRXC_IDLE, 0, TRXC_IDLE, 0 },
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|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
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|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
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|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
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{ TRXC_SACCHTF, 2, TRXC_SACCHTF, 2 },
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|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
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|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
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|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
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|
{ TRXC_IDLE, 0, TRXC_IDLE, 0 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
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|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
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|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
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|
{ TRXC_SACCHTF, 3, TRXC_SACCHTF, 3 },
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|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
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|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_IDLE, 0, TRXC_IDLE, 0 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_TCHF, 0, TRXC_TCHF, 0 }, { TRXC_TCHF, 1, TRXC_TCHF, 1 }, { TRXC_TCHF, 2, TRXC_TCHF, 2 }, { TRXC_TCHF, 3, TRXC_TCHF, 3 },
|
|
{ TRXC_SACCHTF, 0, TRXC_SACCHTF, 0 },
|
|
};
|
|
|
|
static const struct trx_sched_frame frame_tchh_ts01[104] = {
|
|
/* dl_chan dl_bid ul_chan ul_bid */
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_SACCHTH_0, 0, TRXC_SACCHTH_0, 0 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_SACCHTH_1, 0, TRXC_SACCHTH_1, 0 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_SACCHTH_0, 1, TRXC_SACCHTH_0, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_SACCHTH_1, 1, TRXC_SACCHTH_1, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_SACCHTH_0, 2, TRXC_SACCHTH_0, 2 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_SACCHTH_1, 2, TRXC_SACCHTH_1, 2 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_SACCHTH_0, 3, TRXC_SACCHTH_0, 3 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_SACCHTH_1, 3, TRXC_SACCHTH_1, 3 },
|
|
};
|
|
|
|
static const struct trx_sched_frame frame_tchh_ts23[104] = {
|
|
/* dl_chan dl_bid ul_chan ul_bid */
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_SACCHTH_0, 3, TRXC_SACCHTH_0, 3 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_SACCHTH_1, 3, TRXC_SACCHTH_1, 3 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_SACCHTH_0, 0, TRXC_SACCHTH_0, 0 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_SACCHTH_1, 0, TRXC_SACCHTH_1, 0 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_SACCHTH_0, 1, TRXC_SACCHTH_0, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_SACCHTH_1, 1, TRXC_SACCHTH_1, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
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|
{ TRXC_SACCHTH_0, 2, TRXC_SACCHTH_0, 2 },
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|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
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|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
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|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
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{ TRXC_SACCHTH_1, 2, TRXC_SACCHTH_1, 2 },
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|
};
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|
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|
static const struct trx_sched_frame frame_tchh_ts45[104] = {
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|
/* dl_chan dl_bid ul_chan ul_bid */
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|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
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{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
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{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
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{ TRXC_SACCHTH_0, 2, TRXC_SACCHTH_0, 2 },
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{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
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{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
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{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
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{ TRXC_SACCHTH_1, 2, TRXC_SACCHTH_1, 2 },
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{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
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{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
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{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
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{ TRXC_SACCHTH_0, 3, TRXC_SACCHTH_0, 3 },
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|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
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{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
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{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
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{ TRXC_SACCHTH_1, 3, TRXC_SACCHTH_1, 3 },
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|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
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|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
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|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
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{ TRXC_SACCHTH_0, 0, TRXC_SACCHTH_0, 0 },
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|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
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|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
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|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_SACCHTH_1, 0, TRXC_SACCHTH_1, 0 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_SACCHTH_0, 1, TRXC_SACCHTH_0, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_SACCHTH_1, 1, TRXC_SACCHTH_1, 1 },
|
|
};
|
|
|
|
static const struct trx_sched_frame frame_tchh_ts67[104] = {
|
|
/* dl_chan dl_bid ul_chan ul_bid */
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_SACCHTH_0, 1, TRXC_SACCHTH_0, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_SACCHTH_1, 1, TRXC_SACCHTH_1, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_SACCHTH_0, 2, TRXC_SACCHTH_0, 2 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_SACCHTH_1, 2, TRXC_SACCHTH_1, 2 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_SACCHTH_0, 3, TRXC_SACCHTH_0, 3 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_SACCHTH_1, 3, TRXC_SACCHTH_1, 3 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_SACCHTH_0, 0, TRXC_SACCHTH_0, 0 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 }, { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 }, { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 }, { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
|
|
{ TRXC_SACCHTH_1, 0, TRXC_SACCHTH_1, 0 },
|
|
};
|
|
|
|
static const struct trx_sched_frame frame_pdch[104] = {
|
|
/* dl_chan dl_bid ul_chan ul_bid */
|
|
{ TRXC_PDTCH, 0, TRXC_PDTCH, 0 }, { TRXC_PDTCH, 1, TRXC_PDTCH, 1 }, { TRXC_PDTCH, 2, TRXC_PDTCH, 2 }, { TRXC_PDTCH, 3, TRXC_PDTCH, 3 },
|
|
{ TRXC_PDTCH, 0, TRXC_PDTCH, 0 }, { TRXC_PDTCH, 1, TRXC_PDTCH, 1 }, { TRXC_PDTCH, 2, TRXC_PDTCH, 2 }, { TRXC_PDTCH, 3, TRXC_PDTCH, 3 },
|
|
{ TRXC_PDTCH, 0, TRXC_PDTCH, 0 }, { TRXC_PDTCH, 1, TRXC_PDTCH, 1 }, { TRXC_PDTCH, 2, TRXC_PDTCH, 2 }, { TRXC_PDTCH, 3, TRXC_PDTCH, 3 },
|
|
{ TRXC_PTCCH, 0, TRXC_PTCCH, 0 },
|
|
{ TRXC_PDTCH, 0, TRXC_PDTCH, 0 }, { TRXC_PDTCH, 1, TRXC_PDTCH, 1 }, { TRXC_PDTCH, 2, TRXC_PDTCH, 2 }, { TRXC_PDTCH, 3, TRXC_PDTCH, 3 },
|
|
{ TRXC_PDTCH, 0, TRXC_PDTCH, 0 }, { TRXC_PDTCH, 1, TRXC_PDTCH, 1 }, { TRXC_PDTCH, 2, TRXC_PDTCH, 2 }, { TRXC_PDTCH, 3, TRXC_PDTCH, 3 },
|
|
{ TRXC_PDTCH, 0, TRXC_PDTCH, 0 }, { TRXC_PDTCH, 1, TRXC_PDTCH, 1 }, { TRXC_PDTCH, 2, TRXC_PDTCH, 2 }, { TRXC_PDTCH, 3, TRXC_PDTCH, 3 },
|
|
{ TRXC_IDLE, 0, TRXC_IDLE, 0 },
|
|
{ TRXC_PDTCH, 0, TRXC_PDTCH, 0 }, { TRXC_PDTCH, 1, TRXC_PDTCH, 1 }, { TRXC_PDTCH, 2, TRXC_PDTCH, 2 }, { TRXC_PDTCH, 3, TRXC_PDTCH, 3 },
|
|
{ TRXC_PDTCH, 0, TRXC_PDTCH, 0 }, { TRXC_PDTCH, 1, TRXC_PDTCH, 1 }, { TRXC_PDTCH, 2, TRXC_PDTCH, 2 }, { TRXC_PDTCH, 3, TRXC_PDTCH, 3 },
|
|
{ TRXC_PDTCH, 0, TRXC_PDTCH, 0 }, { TRXC_PDTCH, 1, TRXC_PDTCH, 1 }, { TRXC_PDTCH, 2, TRXC_PDTCH, 2 }, { TRXC_PDTCH, 3, TRXC_PDTCH, 3 },
|
|
{ TRXC_PTCCH, 1, TRXC_PTCCH, 1 },
|
|
{ TRXC_PDTCH, 0, TRXC_PDTCH, 0 }, { TRXC_PDTCH, 1, TRXC_PDTCH, 1 }, { TRXC_PDTCH, 2, TRXC_PDTCH, 2 }, { TRXC_PDTCH, 3, TRXC_PDTCH, 3 },
|
|
{ TRXC_PDTCH, 0, TRXC_PDTCH, 0 }, { TRXC_PDTCH, 1, TRXC_PDTCH, 1 }, { TRXC_PDTCH, 2, TRXC_PDTCH, 2 }, { TRXC_PDTCH, 3, TRXC_PDTCH, 3 },
|
|
{ TRXC_PDTCH, 0, TRXC_PDTCH, 0 }, { TRXC_PDTCH, 1, TRXC_PDTCH, 1 }, { TRXC_PDTCH, 2, TRXC_PDTCH, 2 }, { TRXC_PDTCH, 3, TRXC_PDTCH, 3 },
|
|
{ TRXC_IDLE, 0, TRXC_IDLE, 0 },
|
|
{ TRXC_PDTCH, 0, TRXC_PDTCH, 0 }, { TRXC_PDTCH, 1, TRXC_PDTCH, 1 }, { TRXC_PDTCH, 2, TRXC_PDTCH, 2 }, { TRXC_PDTCH, 3, TRXC_PDTCH, 3 },
|
|
{ TRXC_PDTCH, 0, TRXC_PDTCH, 0 }, { TRXC_PDTCH, 1, TRXC_PDTCH, 1 }, { TRXC_PDTCH, 2, TRXC_PDTCH, 2 }, { TRXC_PDTCH, 3, TRXC_PDTCH, 3 },
|
|
{ TRXC_PDTCH, 0, TRXC_PDTCH, 0 }, { TRXC_PDTCH, 1, TRXC_PDTCH, 1 }, { TRXC_PDTCH, 2, TRXC_PDTCH, 2 }, { TRXC_PDTCH, 3, TRXC_PDTCH, 3 },
|
|
{ TRXC_PTCCH, 2, TRXC_PTCCH, 2 },
|
|
{ TRXC_PDTCH, 0, TRXC_PDTCH, 0 }, { TRXC_PDTCH, 1, TRXC_PDTCH, 1 }, { TRXC_PDTCH, 2, TRXC_PDTCH, 2 }, { TRXC_PDTCH, 3, TRXC_PDTCH, 3 },
|
|
{ TRXC_PDTCH, 0, TRXC_PDTCH, 0 }, { TRXC_PDTCH, 1, TRXC_PDTCH, 1 }, { TRXC_PDTCH, 2, TRXC_PDTCH, 2 }, { TRXC_PDTCH, 3, TRXC_PDTCH, 3 },
|
|
{ TRXC_PDTCH, 0, TRXC_PDTCH, 0 }, { TRXC_PDTCH, 1, TRXC_PDTCH, 1 }, { TRXC_PDTCH, 2, TRXC_PDTCH, 2 }, { TRXC_PDTCH, 3, TRXC_PDTCH, 3 },
|
|
{ TRXC_IDLE, 0, TRXC_IDLE, 0 },
|
|
{ TRXC_PDTCH, 0, TRXC_PDTCH, 0 }, { TRXC_PDTCH, 1, TRXC_PDTCH, 1 }, { TRXC_PDTCH, 2, TRXC_PDTCH, 2 }, { TRXC_PDTCH, 3, TRXC_PDTCH, 3 },
|
|
{ TRXC_PDTCH, 0, TRXC_PDTCH, 0 }, { TRXC_PDTCH, 1, TRXC_PDTCH, 1 }, { TRXC_PDTCH, 2, TRXC_PDTCH, 2 }, { TRXC_PDTCH, 3, TRXC_PDTCH, 3 },
|
|
{ TRXC_PDTCH, 0, TRXC_PDTCH, 0 }, { TRXC_PDTCH, 1, TRXC_PDTCH, 1 }, { TRXC_PDTCH, 2, TRXC_PDTCH, 2 }, { TRXC_PDTCH, 3, TRXC_PDTCH, 3 },
|
|
{ TRXC_PTCCH, 3, TRXC_PTCCH, 3 },
|
|
{ TRXC_PDTCH, 0, TRXC_PDTCH, 0 }, { TRXC_PDTCH, 1, TRXC_PDTCH, 1 }, { TRXC_PDTCH, 2, TRXC_PDTCH, 2 }, { TRXC_PDTCH, 3, TRXC_PDTCH, 3 },
|
|
{ TRXC_PDTCH, 0, TRXC_PDTCH, 0 }, { TRXC_PDTCH, 1, TRXC_PDTCH, 1 }, { TRXC_PDTCH, 2, TRXC_PDTCH, 2 }, { TRXC_PDTCH, 3, TRXC_PDTCH, 3 },
|
|
{ TRXC_PDTCH, 0, TRXC_PDTCH, 0 }, { TRXC_PDTCH, 1, TRXC_PDTCH, 1 }, { TRXC_PDTCH, 2, TRXC_PDTCH, 2 }, { TRXC_PDTCH, 3, TRXC_PDTCH, 3 },
|
|
{ TRXC_IDLE, 0, TRXC_IDLE, 0 },
|
|
};
|
|
|
|
const struct trx_sched_multiframe trx_sched_multiframes[] = {
|
|
{ GSM_PCHAN_NONE, 0xff, 0, NULL, "NONE"},
|
|
{ GSM_PCHAN_CCCH, 0xff, 51, frame_bcch, "BCCH+CCCH" },
|
|
{ GSM_PCHAN_CCCH_SDCCH4, 0xff, 102, frame_bcch_sdcch4, "BCCH+CCCH+SDCCH/4+SACCH/4" },
|
|
{ GSM_PCHAN_CCCH_SDCCH4_CBCH, 0xff, 102, frame_bcch_sdcch4_cbch, "BCCH+CCCH+SDCCH/4+SACCH/4+CBCH" },
|
|
{ GSM_PCHAN_SDCCH8_SACCH8C, 0xff, 102, frame_sdcch8, "SDCCH/8+SACCH/8" },
|
|
{ GSM_PCHAN_SDCCH8_SACCH8C_CBCH,0xff, 102, frame_sdcch8_cbch, "SDCCH/8+SACCH/8+CBCH" },
|
|
{ GSM_PCHAN_TCH_F, 0x01, 104, frame_tchf_ts0, "TCH/F+SACCH" },
|
|
{ GSM_PCHAN_TCH_F, 0x02, 104, frame_tchf_ts1, "TCH/F+SACCH" },
|
|
{ GSM_PCHAN_TCH_F, 0x04, 104, frame_tchf_ts2, "TCH/F+SACCH" },
|
|
{ GSM_PCHAN_TCH_F, 0x08, 104, frame_tchf_ts3, "TCH/F+SACCH" },
|
|
{ GSM_PCHAN_TCH_F, 0x10, 104, frame_tchf_ts4, "TCH/F+SACCH" },
|
|
{ GSM_PCHAN_TCH_F, 0x20, 104, frame_tchf_ts5, "TCH/F+SACCH" },
|
|
{ GSM_PCHAN_TCH_F, 0x40, 104, frame_tchf_ts6, "TCH/F+SACCH" },
|
|
{ GSM_PCHAN_TCH_F, 0x80, 104, frame_tchf_ts7, "TCH/F+SACCH" },
|
|
{ GSM_PCHAN_TCH_H, 0x03, 104, frame_tchh_ts01, "TCH/H+SACCH" },
|
|
{ GSM_PCHAN_TCH_H, 0x0c, 104, frame_tchh_ts23, "TCH/H+SACCH" },
|
|
{ GSM_PCHAN_TCH_H, 0x30, 104, frame_tchh_ts45, "TCH/H+SACCH" },
|
|
{ GSM_PCHAN_TCH_H, 0xc0, 104, frame_tchh_ts67, "TCH/H+SACCH" },
|
|
{ GSM_PCHAN_PDCH, 0xff, 104, frame_pdch, "PDCH" },
|
|
};
|
|
|
|
|
|
/*
|
|
* scheduler functions
|
|
*/
|
|
|
|
int find_sched_mframe_idx(enum gsm_phys_chan_config pchan, uint8_t tn)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(trx_sched_multiframes); i++) {
|
|
if (trx_sched_multiframes[i].pchan == pchan
|
|
&& (trx_sched_multiframes[i].slotmask & (1 << tn))) {
|
|
return i;
|
|
}
|
|
}
|
|
return -1;
|
|
}
|
|
|
|
/* Determine if given frame number contains SACCH (true) or other (false) burst */
|
|
bool trx_sched_is_sacch_fn(const struct gsm_bts_trx_ts *ts, uint32_t fn, bool uplink)
|
|
{
|
|
int i;
|
|
const struct trx_sched_multiframe *sched;
|
|
const struct trx_sched_frame *frame;
|
|
enum trx_chan_type ch_type;
|
|
|
|
i = find_sched_mframe_idx(ts_pchan(ts), ts->nr);
|
|
if (i < 0)
|
|
return -EINVAL;
|
|
sched = &trx_sched_multiframes[i];
|
|
frame = &sched->frames[fn % sched->period];
|
|
if (uplink)
|
|
ch_type = frame->ul_chan;
|
|
else
|
|
ch_type = frame->dl_chan;
|
|
|
|
switch (ch_type) {
|
|
case TRXC_SACCH4_0:
|
|
case TRXC_SACCH4_1:
|
|
case TRXC_SACCH4_2:
|
|
case TRXC_SACCH4_3:
|
|
case TRXC_SACCH8_0:
|
|
case TRXC_SACCH8_1:
|
|
case TRXC_SACCH8_2:
|
|
case TRXC_SACCH8_3:
|
|
case TRXC_SACCH8_4:
|
|
case TRXC_SACCH8_5:
|
|
case TRXC_SACCH8_6:
|
|
case TRXC_SACCH8_7:
|
|
case TRXC_SACCHTF:
|
|
case TRXC_SACCHTH_0:
|
|
case TRXC_SACCHTH_1:
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|