TRX: factor out the scheduler from remaining code
The L1 scheduler is a generally useful component that is unfortunately tied quite a bit into the OsmoTRX support. Let's try to separate it out by having separate per-trx/per-ts/per-chan data structures pre-fixed with l1sched_ Using this patch it should be one step easier to use the scheduler for other BTS models, such as the intended upcoming virtual BTS.
This commit is contained in:
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@ -68,9 +68,10 @@ struct trx_l1h *l1if_open(struct gsm_bts_trx *trx)
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if (!l1h)
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return NULL;
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l1h->trx = trx;
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l1h->l1s.trx = trx;
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trx->role_bts.l1h = l1h;
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trx_sched_init(l1h);
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trx_sched_init(&l1h->l1s);
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rc = trx_if_open(l1h);
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if (rc < 0) {
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@ -89,7 +90,7 @@ err:
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void l1if_close(struct trx_l1h *l1h)
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{
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trx_if_close(l1h);
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trx_sched_exit(l1h);
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trx_sched_exit(&l1h->l1s);
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talloc_free(l1h);
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}
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@ -267,7 +268,7 @@ int bts_model_trx_close(struct gsm_bts_trx *trx)
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enum gsm_phys_chan_config pchan = trx->ts[0].pchan;
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/* close all logical channels and reset timeslots */
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trx_sched_reset(l1h);
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trx_sched_reset(&l1h->l1s);
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/* deactivate lchan for CCCH */
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if (pchan == GSM_PCHAN_CCCH || pchan == GSM_PCHAN_CCCH_SDCCH4) {
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@ -374,8 +375,12 @@ static uint8_t trx_set_ts(struct gsm_bts_trx_ts *ts)
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l1if_provision_transceiver_trx(l1h);
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}
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/* ignore disabled slots */
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if (!(l1h->config.slotmask & (1 << tn)))
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return NM_NACK_RES_NOTAVAIL;
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/* set physical channel */
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rc = trx_sched_set_pchan(l1h, tn, pchan);
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rc = trx_sched_set_pchan(&l1h->l1s, tn, pchan);
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if (rc)
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return NM_NACK_RES_NOTAVAIL;
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@ -413,17 +418,17 @@ static int l1if_set_ciphering(struct trx_l1h *l1h, struct gsm_lchan *lchan,
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if (!downlink) {
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/* set uplink */
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trx_sched_set_cipher(l1h, chan_nr, 0, lchan->encr.alg_id - 1,
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trx_sched_set_cipher(&l1h->l1s, chan_nr, 0, lchan->encr.alg_id - 1,
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lchan->encr.key, lchan->encr.key_len);
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lchan->ciph_state = LCHAN_CIPH_RX_CONF;
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} else {
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/* set downlink and also set uplink, if not already */
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if (lchan->ciph_state != LCHAN_CIPH_RX_CONF) {
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trx_sched_set_cipher(l1h, chan_nr, 0,
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trx_sched_set_cipher(&l1h->l1s, chan_nr, 0,
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lchan->encr.alg_id - 1, lchan->encr.key,
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lchan->encr.key_len);
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}
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trx_sched_set_cipher(l1h, chan_nr, 1, lchan->encr.alg_id - 1,
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trx_sched_set_cipher(&l1h->l1s, chan_nr, 1, lchan->encr.alg_id - 1,
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lchan->encr.key, lchan->encr.key_len);
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lchan->ciph_state = LCHAN_CIPH_RXTX_CONF;
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}
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@ -510,12 +515,12 @@ int bts_model_l1sap_down(struct gsm_bts_trx *trx, struct osmo_phsap_prim *l1sap)
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if (!msg)
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break;
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/* put data into scheduler's queue */
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return trx_sched_ph_data_req(l1h, l1sap);
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return trx_sched_ph_data_req(&l1h->l1s, l1sap);
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case OSMO_PRIM(PRIM_TCH, PRIM_OP_REQUEST):
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if (!msg)
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break;
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/* put data into scheduler's queue */
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return trx_sched_tch_req(l1h, l1sap);
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return trx_sched_tch_req(&l1h->l1s, l1sap);
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case OSMO_PRIM(PRIM_MPH_INFO, PRIM_OP_REQUEST):
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switch (l1sap->u.info.type) {
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case PRIM_INFO_ACT_CIPH:
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@ -542,11 +547,11 @@ int bts_model_l1sap_down(struct gsm_bts_trx *trx, struct osmo_phsap_prim *l1sap)
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break;
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}
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/* activate dedicated channel */
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trx_sched_set_lchan(l1h, chan_nr, 0x00, 1);
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trx_sched_set_lchan(&l1h->l1s, chan_nr, 0x00, 1);
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/* activate associated channel */
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trx_sched_set_lchan(l1h, chan_nr, 0x40, 1);
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trx_sched_set_lchan(&l1h->l1s, chan_nr, 0x40, 1);
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/* set mode */
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trx_sched_set_mode(l1h, chan_nr,
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trx_sched_set_mode(&l1h->l1s, chan_nr,
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lchan->rsl_cmode, lchan->tch_mode,
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lchan->tch.amr_mr.num_modes,
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lchan->tch.amr_mr.bts_mode[0].mode,
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@ -574,7 +579,7 @@ int bts_model_l1sap_down(struct gsm_bts_trx *trx, struct osmo_phsap_prim *l1sap)
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}
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if (l1sap->u.info.type == PRIM_INFO_MODIFY) {
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/* change mode */
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trx_sched_set_mode(l1h, chan_nr,
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trx_sched_set_mode(&l1h->l1s, chan_nr,
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lchan->rsl_cmode, lchan->tch_mode,
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lchan->tch.amr_mr.num_modes,
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lchan->tch.amr_mr.bts_mode[0].mode,
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@ -591,12 +596,12 @@ int bts_model_l1sap_down(struct gsm_bts_trx *trx, struct osmo_phsap_prim *l1sap)
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break;
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}
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/* deactivate associated channel */
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trx_sched_set_lchan(l1h, chan_nr, 0x40, 0);
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trx_sched_set_lchan(&l1h->l1s, chan_nr, 0x40, 0);
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if (!l1sap->u.info.u.act_req.sacch_only) {
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/* set lchan inactive */
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lchan_set_state(lchan, LCHAN_S_NONE);
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/* deactivate dedicated channel */
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trx_sched_set_lchan(l1h, chan_nr, 0x00, 0);
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trx_sched_set_lchan(&l1h->l1s, chan_nr, 0x00, 0);
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/* confirm only on dedicated channel */
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mph_info_chan_confirm(l1h, chan_nr,
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PRIM_INFO_DEACTIVATE, 0);
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@ -1,109 +1,7 @@
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#ifndef L1_IF_H_TRX
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#define L1_IF_H_TRX
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/* These types define the different channels on a multiframe.
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* Each channel has queues and can be activated individually.
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*/
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enum trx_chan_type {
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TRXC_IDLE = 0,
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TRXC_FCCH,
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TRXC_SCH,
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TRXC_BCCH,
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TRXC_RACH,
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TRXC_CCCH,
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TRXC_TCHF,
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TRXC_TCHH_0,
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TRXC_TCHH_1,
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TRXC_SDCCH4_0,
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TRXC_SDCCH4_1,
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TRXC_SDCCH4_2,
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TRXC_SDCCH4_3,
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TRXC_SDCCH8_0,
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TRXC_SDCCH8_1,
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TRXC_SDCCH8_2,
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TRXC_SDCCH8_3,
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TRXC_SDCCH8_4,
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TRXC_SDCCH8_5,
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TRXC_SDCCH8_6,
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TRXC_SDCCH8_7,
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TRXC_SACCHTF,
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TRXC_SACCHTH_0,
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TRXC_SACCHTH_1,
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TRXC_SACCH4_0,
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TRXC_SACCH4_1,
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TRXC_SACCH4_2,
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TRXC_SACCH4_3,
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TRXC_SACCH8_0,
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TRXC_SACCH8_1,
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TRXC_SACCH8_2,
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TRXC_SACCH8_3,
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TRXC_SACCH8_4,
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TRXC_SACCH8_5,
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TRXC_SACCH8_6,
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TRXC_SACCH8_7,
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TRXC_PDTCH,
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TRXC_PTCCH,
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_TRX_CHAN_MAX
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};
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/* States each channel on a multiframe */
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struct trx_chan_state {
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/* scheduler */
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uint8_t active; /* Channel is active */
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ubit_t *dl_bursts; /* burst buffer for TX */
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sbit_t *ul_bursts; /* burst buffer for RX */
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uint32_t ul_first_fn; /* fn of first burst */
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uint8_t ul_mask; /* mask of received bursts */
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/* RSSI / TOA */
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uint8_t rssi_num; /* number of RSSI values */
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float rssi_sum; /* sum of RSSI values */
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uint8_t toa_num; /* number of TOA values */
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float toa_sum; /* sum of TOA values */
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/* loss detection */
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uint8_t lost; /* (SACCH) loss detection */
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/* mode */
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uint8_t rsl_cmode, tch_mode; /* mode for TCH channels */
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/* AMR */
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uint8_t codec[4]; /* 4 possible codecs for amr */
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int codecs; /* number of possible codecs */
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float ber_sum; /* sum of bit error rates */
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int ber_num; /* number of bit error rates */
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uint8_t ul_ft; /* current uplink FT index */
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uint8_t dl_ft; /* current downlink FT index */
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uint8_t ul_cmr; /* current uplink CMR index */
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uint8_t dl_cmr; /* current downlink CMR index */
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uint8_t amr_loop; /* if AMR loop is enabled */
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/* TCH/H */
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uint8_t dl_ongoing_facch; /* FACCH/H on downlink */
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uint8_t ul_ongoing_facch; /* FACCH/H on uplink */
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/* encryption */
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int ul_encr_algo; /* A5/x encry algo downlink */
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int dl_encr_algo; /* A5/x encry algo uplink */
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int ul_encr_key_len;
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int dl_encr_key_len;
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uint8_t ul_encr_key[MAX_A5_KEY_LEN];
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uint8_t dl_encr_key[MAX_A5_KEY_LEN];
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/* measurements */
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struct {
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uint8_t clock; /* cyclic clock counter */
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int8_t rssi[32]; /* last RSSI values */
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int rssi_count; /* received RSSI values */
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int rssi_valid_count; /* number of stored value */
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int rssi_got_burst; /* any burst received so far */
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float toa_sum; /* sum of TOA values */
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int toa_num; /* number of TOA value */
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} meas;
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/* handover */
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uint8_t ho_rach_detect; /* if rach detection is on */
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};
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#include "scheduler.h"
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struct trx_config {
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uint8_t poweron; /* poweron(1) or poweroff(0) */
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@ -152,16 +50,9 @@ struct trx_l1h {
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/* transceiver config */
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struct trx_config config;
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uint8_t mf_index[TRX_NR_TS]; /* selected multiframe index */
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uint32_t mf_last_fn[TRX_NR_TS]; /* last received frame */
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uint8_t mf_period[TRX_NR_TS]; /* period of multiframe */
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const struct trx_sched_frame *mf_frames[TRX_NR_TS]; /* pointer to frame layout */
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/* Channel states for all channels on all timeslots */
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struct trx_chan_state chan_states[TRX_NR_TS][_TRX_CHAN_MAX];
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struct llist_head dl_prims[TRX_NR_TS]; /* Queue primitves for TX */
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uint8_t ho_rach_detect[TRX_NR_TS][TS_MAX_LCHAN];
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struct l1sched_trx l1s;
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};
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struct trx_l1h *l1if_open(struct gsm_bts_trx *trx);
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@ -176,4 +67,10 @@ void l1if_fill_meas_res(struct osmo_phsap_prim *l1sap, uint8_t chan_nr, float ta
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int l1if_process_meas_res(struct gsm_bts_trx *trx, uint8_t tn, uint32_t fn, uint8_t chan_nr,
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int n_errors, int n_bits_total, float rssi, float toa);
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static inline struct l1sched_trx *trx_l1sched_hdl(struct gsm_bts_trx *trx)
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{
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struct trx_l1h *l1h = trx_l1h_hdl(trx);
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return &l1h->l1s;
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}
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#endif /* L1_IF_H_TRX */
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@ -33,7 +33,7 @@
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#include "l1_if.h"
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#include "loops.h"
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#define MS_PWR_DBM(lvl) ms_pwr_dbm(gsm_arfcn2band(l1h->config.arfcn), lvl)
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#define MS_PWR_DBM(arfcn, lvl) ms_pwr_dbm(gsm_arfcn2band(arfcn), lvl)
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/*
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* MS Power loop
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@ -42,11 +42,12 @@
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int trx_ms_power_loop = 0;
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int8_t trx_target_rssi = -10;
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static int ms_power_diff(struct trx_l1h *l1h, struct gsm_lchan *lchan,
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uint8_t chan_nr, struct trx_chan_state *chan_state, int8_t diff)
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static int ms_power_diff(struct gsm_lchan *lchan, uint8_t chan_nr, int8_t diff)
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{
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struct gsm_bts_trx *trx = lchan->ts->trx;
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uint16_t arfcn = trx->arfcn;
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int8_t new_power;
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new_power = lchan->ms_power - (diff >> 1);
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if (diff == 0)
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@ -56,7 +57,7 @@ static int ms_power_diff(struct trx_l1h *l1h, struct gsm_lchan *lchan,
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new_power = 0;
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// FIXME: to go above 1W, we need to know classmark of MS
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if (l1h->config.arfcn >= 512 && l1h->config.arfcn <= 885) {
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if (arfcn >= 512 && arfcn <= 885) {
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if (new_power > 15)
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new_power = 15;
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} else {
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@ -73,8 +74,8 @@ static int ms_power_diff(struct trx_l1h *l1h, struct gsm_lchan *lchan,
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if (lchan->ms_power == new_power) {
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LOGP(DLOOP, LOGL_INFO, "Keeping MS new_power of trx=%u "
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"chan_nr=0x%02x at control level %d (%d dBm)\n",
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l1h->trx->nr, chan_nr, new_power,
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MS_PWR_DBM(new_power));
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trx->nr, chan_nr, new_power,
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MS_PWR_DBM(arfcn, new_power));
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return 0;
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}
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@ -82,15 +83,16 @@ static int ms_power_diff(struct trx_l1h *l1h, struct gsm_lchan *lchan,
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LOGP(DLOOP, LOGL_INFO, "%s MS new_power of trx=%u chan_nr=0x%02x from "
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"control level %d (%d dBm) to %d (%d dBm)\n",
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(diff > 0) ? "Raising" : "Lowering",
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l1h->trx->nr, chan_nr, lchan->ms_power,
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MS_PWR_DBM(lchan->ms_power), new_power, MS_PWR_DBM(new_power));
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trx->nr, chan_nr, lchan->ms_power,
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MS_PWR_DBM(arfcn, lchan->ms_power), new_power,
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MS_PWR_DBM(arfcn, new_power));
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lchan->ms_power = new_power;
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return 0;
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}
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static int ms_power_val(struct trx_chan_state *chan_state, int8_t rssi)
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static int ms_power_val(struct l1sched_chan_state *chan_state, int8_t rssi)
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{
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/* ignore inserted dummy frames, treat as lost frames */
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if (rssi < -127)
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@ -112,9 +114,10 @@ static int ms_power_val(struct trx_chan_state *chan_state, int8_t rssi)
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return 0;
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}
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static int ms_power_clock(struct trx_l1h *l1h, struct gsm_lchan *lchan,
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uint8_t chan_nr, struct trx_chan_state *chan_state)
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static int ms_power_clock(struct gsm_lchan *lchan,
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uint8_t chan_nr, struct l1sched_chan_state *chan_state)
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{
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struct gsm_bts_trx *trx = lchan->ts->trx;
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int rssi;
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int i;
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@ -134,9 +137,8 @@ static int ms_power_clock(struct trx_l1h *l1h, struct gsm_lchan *lchan,
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if (chan_state->meas.rssi_count == 0) {
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LOGP(DLOOP, LOGL_NOTICE, "LOST SACCH frame of trx=%u "
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"chan_nr=0x%02x, so we raise MS power\n",
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l1h->trx->nr, chan_nr);
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return ms_power_diff(l1h, lchan, chan_nr, chan_state,
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MS_RAISE_MAX);
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trx->nr, chan_nr);
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return ms_power_diff(lchan, chan_nr, MS_RAISE_MAX);
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}
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/* reset total counter */
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@ -157,9 +159,10 @@ static int ms_power_clock(struct trx_l1h *l1h, struct gsm_lchan *lchan,
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/* change RSSI */
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LOGP(DLOOP, LOGL_DEBUG, "Lowest RSSI: %d Target RSSI: %d Current "
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"MS power: %d (%d dBm) of trx=%u chan_nr=0x%02x\n", rssi,
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trx_target_rssi, lchan->ms_power, MS_PWR_DBM(lchan->ms_power),
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l1h->trx->nr, chan_nr);
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ms_power_diff(l1h, lchan, chan_nr, chan_state, trx_target_rssi - rssi);
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trx_target_rssi, lchan->ms_power,
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MS_PWR_DBM(trx->arfcn, lchan->ms_power),
|
||||
trx->nr, chan_nr);
|
||||
ms_power_diff(lchan, chan_nr, trx_target_rssi - rssi);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -171,9 +174,11 @@ static int ms_power_clock(struct trx_l1h *l1h, struct gsm_lchan *lchan,
|
|||
|
||||
int trx_ta_loop = 1;
|
||||
|
||||
int ta_val(struct trx_l1h *l1h, struct gsm_lchan *lchan, uint8_t chan_nr,
|
||||
struct trx_chan_state *chan_state, float toa)
|
||||
int ta_val(struct gsm_lchan *lchan, uint8_t chan_nr,
|
||||
struct l1sched_chan_state *chan_state, float toa)
|
||||
{
|
||||
struct gsm_bts_trx *trx = lchan->ts->trx;
|
||||
|
||||
/* check if the current L1 header acks to the current ordered TA */
|
||||
if (lchan->meas.l1_info[1] != lchan->rqd_ta)
|
||||
return 0;
|
||||
|
@ -190,19 +195,19 @@ int ta_val(struct trx_l1h *l1h, struct gsm_lchan *lchan, uint8_t chan_nr,
|
|||
if (toa < -0.9F && lchan->rqd_ta > 0) {
|
||||
LOGP(DLOOP, LOGL_INFO, "TOA of trx=%u chan_nr=0x%02x is too "
|
||||
"early (%.2f), now lowering TA from %d to %d\n",
|
||||
l1h->trx->nr, chan_nr, toa, lchan->rqd_ta,
|
||||
trx->nr, chan_nr, toa, lchan->rqd_ta,
|
||||
lchan->rqd_ta - 1);
|
||||
lchan->rqd_ta--;
|
||||
} else if (toa > 0.9F && lchan->rqd_ta < 63) {
|
||||
LOGP(DLOOP, LOGL_INFO, "TOA of trx=%u chan_nr=0x%02x is too "
|
||||
"late (%.2f), now raising TA from %d to %d\n",
|
||||
l1h->trx->nr, chan_nr, toa, lchan->rqd_ta,
|
||||
trx->nr, chan_nr, toa, lchan->rqd_ta,
|
||||
lchan->rqd_ta + 1);
|
||||
lchan->rqd_ta++;
|
||||
} else
|
||||
LOGP(DLOOP, LOGL_INFO, "TOA of trx=%u chan_nr=0x%02x is "
|
||||
"correct (%.2f), keeping current TA of %d\n",
|
||||
l1h->trx->nr, chan_nr, toa, lchan->rqd_ta);
|
||||
trx->nr, chan_nr, toa, lchan->rqd_ta);
|
||||
|
||||
chan_state->meas.toa_num = 0;
|
||||
chan_state->meas.toa_sum = 0;
|
||||
|
@ -210,29 +215,29 @@ int ta_val(struct trx_l1h *l1h, struct gsm_lchan *lchan, uint8_t chan_nr,
|
|||
return 0;
|
||||
}
|
||||
|
||||
int trx_loop_sacch_input(struct trx_l1h *l1h, uint8_t chan_nr,
|
||||
struct trx_chan_state *chan_state, int8_t rssi, float toa)
|
||||
int trx_loop_sacch_input(struct l1sched_trx *l1t, uint8_t chan_nr,
|
||||
struct l1sched_chan_state *chan_state, int8_t rssi, float toa)
|
||||
{
|
||||
struct gsm_lchan *lchan = &l1h->trx->ts[L1SAP_CHAN2TS(chan_nr)]
|
||||
struct gsm_lchan *lchan = &l1t->trx->ts[L1SAP_CHAN2TS(chan_nr)]
|
||||
.lchan[l1sap_chan2ss(chan_nr)];
|
||||
|
||||
if (trx_ms_power_loop)
|
||||
ms_power_val(chan_state, rssi);
|
||||
|
||||
if (trx_ta_loop)
|
||||
ta_val(l1h, lchan, chan_nr, chan_state, toa);
|
||||
ta_val(lchan, chan_nr, chan_state, toa);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int trx_loop_sacch_clock(struct trx_l1h *l1h, uint8_t chan_nr,
|
||||
struct trx_chan_state *chan_state)
|
||||
int trx_loop_sacch_clock(struct l1sched_trx *l1t, uint8_t chan_nr,
|
||||
struct l1sched_chan_state *chan_state)
|
||||
{
|
||||
struct gsm_lchan *lchan = &l1h->trx->ts[L1SAP_CHAN2TS(chan_nr)]
|
||||
struct gsm_lchan *lchan = &l1t->trx->ts[L1SAP_CHAN2TS(chan_nr)]
|
||||
.lchan[l1sap_chan2ss(chan_nr)];
|
||||
|
||||
if (trx_ms_power_loop)
|
||||
ms_power_clock(l1h, lchan, chan_nr, chan_state);
|
||||
ms_power_clock(lchan, chan_nr, chan_state);
|
||||
|
||||
/* count the number of SACCH clocks */
|
||||
chan_state->meas.clock++;
|
||||
|
@ -240,10 +245,11 @@ int trx_loop_sacch_clock(struct trx_l1h *l1h, uint8_t chan_nr,
|
|||
return 0;
|
||||
}
|
||||
|
||||
int trx_loop_amr_input(struct trx_l1h *l1h, uint8_t chan_nr,
|
||||
struct trx_chan_state *chan_state, float ber)
|
||||
int trx_loop_amr_input(struct l1sched_trx *l1t, uint8_t chan_nr,
|
||||
struct l1sched_chan_state *chan_state, float ber)
|
||||
{
|
||||
struct gsm_lchan *lchan = &l1h->trx->ts[L1SAP_CHAN2TS(chan_nr)]
|
||||
struct gsm_bts_trx *trx = l1t->trx;
|
||||
struct gsm_lchan *lchan = &trx->ts[L1SAP_CHAN2TS(chan_nr)]
|
||||
.lchan[l1sap_chan2ss(chan_nr)];
|
||||
int c_i;
|
||||
|
||||
|
@ -280,7 +286,7 @@ int trx_loop_amr_input(struct trx_l1h *l1h, uint8_t chan_nr,
|
|||
|
||||
LOGP(DLOOP, LOGL_DEBUG, "Current bit error rate (BER) %.6f "
|
||||
"codec id %d of trx=%u chan_nr=0x%02x\n", ber,
|
||||
chan_state->ul_ft, l1h->trx->nr, chan_nr);
|
||||
chan_state->ul_ft, trx->nr, chan_nr);
|
||||
|
||||
/* degrade */
|
||||
if (chan_state->dl_cmr > 0) {
|
||||
|
@ -290,7 +296,7 @@ int trx_loop_amr_input(struct trx_l1h *l1h, uint8_t chan_nr,
|
|||
LOGP(DLOOP, LOGL_DEBUG, "Degrading due to BER %.6f "
|
||||
"from codec id %d to %d of trx=%u "
|
||||
"chan_nr=0x%02x\n", ber, chan_state->dl_cmr,
|
||||
chan_state->dl_cmr - 1, l1h->trx->nr, chan_nr);
|
||||
chan_state->dl_cmr - 1, trx->nr, chan_nr);
|
||||
chan_state->dl_cmr--;
|
||||
}
|
||||
|
||||
|
@ -306,7 +312,7 @@ int trx_loop_amr_input(struct trx_l1h *l1h, uint8_t chan_nr,
|
|||
LOGP(DLOOP, LOGL_DEBUG, "Upgrading due to BER %.6f "
|
||||
"from codec id %d to %d of trx=%u "
|
||||
"chan_nr=0x%02x\n", ber, chan_state->dl_cmr,
|
||||
chan_state->dl_cmr + 1, l1h->trx->nr, chan_nr);
|
||||
chan_state->dl_cmr + 1, trx->nr, chan_nr);
|
||||
chan_state->dl_cmr++;
|
||||
}
|
||||
|
||||
|
@ -316,7 +322,7 @@ int trx_loop_amr_input(struct trx_l1h *l1h, uint8_t chan_nr,
|
|||
return 0;
|
||||
}
|
||||
|
||||
int trx_loop_amr_set(struct trx_chan_state *chan_state, int loop)
|
||||
int trx_loop_amr_set(struct l1sched_chan_state *chan_state, int loop)
|
||||
{
|
||||
if (chan_state->amr_loop && !loop) {
|
||||
chan_state->amr_loop = 0;
|
||||
|
@ -336,4 +342,3 @@ int trx_loop_amr_set(struct trx_chan_state *chan_state, int loop)
|
|||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
@ -17,15 +17,15 @@ extern int trx_ms_power_loop;
|
|||
extern int8_t trx_target_rssi;
|
||||
extern int trx_ta_loop;
|
||||
|
||||
int trx_loop_sacch_input(struct trx_l1h *l1h, uint8_t chan_nr,
|
||||
struct trx_chan_state *chan_state, int8_t rssi, float toa);
|
||||
int trx_loop_sacch_input(struct l1sched_trx *l1t, uint8_t chan_nr,
|
||||
struct l1sched_chan_state *chan_state, int8_t rssi, float toa);
|
||||
|
||||
int trx_loop_sacch_clock(struct trx_l1h *l1h, uint8_t chan_nr,
|
||||
struct trx_chan_state *chan_state);
|
||||
int trx_loop_sacch_clock(struct l1sched_trx *l1t, uint8_t chan_nr,
|
||||
struct l1sched_chan_state *chan_state);
|
||||
|
||||
int trx_loop_amr_input(struct trx_l1h *l1h, uint8_t chan_nr,
|
||||
struct trx_chan_state *chan_state, float ber);
|
||||
int trx_loop_amr_input(struct l1sched_trx *l1t, uint8_t chan_nr,
|
||||
struct l1sched_chan_state *chan_state, float ber);
|
||||
|
||||
int trx_loop_amr_set(struct trx_chan_state *chan_state, int loop);
|
||||
int trx_loop_amr_set(struct l1sched_chan_state *chan_state, int loop);
|
||||
|
||||
#endif /* _TRX_LOOPS_H */
|
||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -1,6 +1,129 @@
|
|||
#ifndef TRX_SCHEDULER_H
|
||||
#define TRX_SCHEDULER_H
|
||||
|
||||
/* These types define the different channels on a multiframe.
|
||||
* Each channel has queues and can be activated individually.
|
||||
*/
|
||||
enum trx_chan_type {
|
||||
TRXC_IDLE = 0,
|
||||
TRXC_FCCH,
|
||||
TRXC_SCH,
|
||||
TRXC_BCCH,
|
||||
TRXC_RACH,
|
||||
TRXC_CCCH,
|
||||
TRXC_TCHF,
|
||||
TRXC_TCHH_0,
|
||||
TRXC_TCHH_1,
|
||||
TRXC_SDCCH4_0,
|
||||
TRXC_SDCCH4_1,
|
||||
TRXC_SDCCH4_2,
|
||||
TRXC_SDCCH4_3,
|
||||
TRXC_SDCCH8_0,
|
||||
TRXC_SDCCH8_1,
|
||||
TRXC_SDCCH8_2,
|
||||
TRXC_SDCCH8_3,
|
||||
TRXC_SDCCH8_4,
|
||||
TRXC_SDCCH8_5,
|
||||
TRXC_SDCCH8_6,
|
||||
TRXC_SDCCH8_7,
|
||||
TRXC_SACCHTF,
|
||||
TRXC_SACCHTH_0,
|
||||
TRXC_SACCHTH_1,
|
||||
TRXC_SACCH4_0,
|
||||
TRXC_SACCH4_1,
|
||||
TRXC_SACCH4_2,
|
||||
TRXC_SACCH4_3,
|
||||
TRXC_SACCH8_0,
|
||||
TRXC_SACCH8_1,
|
||||
TRXC_SACCH8_2,
|
||||
TRXC_SACCH8_3,
|
||||
TRXC_SACCH8_4,
|
||||
TRXC_SACCH8_5,
|
||||
TRXC_SACCH8_6,
|
||||
TRXC_SACCH8_7,
|
||||
TRXC_PDTCH,
|
||||
TRXC_PTCCH,
|
||||
_TRX_CHAN_MAX
|
||||
};
|
||||
|
||||
/* States each channel on a multiframe */
|
||||
struct l1sched_chan_state {
|
||||
/* scheduler */
|
||||
uint8_t active; /* Channel is active */
|
||||
ubit_t *dl_bursts; /* burst buffer for TX */
|
||||
sbit_t *ul_bursts; /* burst buffer for RX */
|
||||
uint32_t ul_first_fn; /* fn of first burst */
|
||||
uint8_t ul_mask; /* mask of received bursts */
|
||||
|
||||
/* RSSI / TOA */
|
||||
uint8_t rssi_num; /* number of RSSI values */
|
||||
float rssi_sum; /* sum of RSSI values */
|
||||
uint8_t toa_num; /* number of TOA values */
|
||||
float toa_sum; /* sum of TOA values */
|
||||
|
||||
/* loss detection */
|
||||
uint8_t lost; /* (SACCH) loss detection */
|
||||
|
||||
/* mode */
|
||||
uint8_t rsl_cmode, tch_mode; /* mode for TCH channels */
|
||||
|
||||
/* AMR */
|
||||
uint8_t codec[4]; /* 4 possible codecs for amr */
|
||||
int codecs; /* number of possible codecs */
|
||||
float ber_sum; /* sum of bit error rates */
|
||||
int ber_num; /* number of bit error rates */
|
||||
uint8_t ul_ft; /* current uplink FT index */
|
||||
uint8_t dl_ft; /* current downlink FT index */
|
||||
uint8_t ul_cmr; /* current uplink CMR index */
|
||||
uint8_t dl_cmr; /* current downlink CMR index */
|
||||
uint8_t amr_loop; /* if AMR loop is enabled */
|
||||
|
||||
/* TCH/H */
|
||||
uint8_t dl_ongoing_facch; /* FACCH/H on downlink */
|
||||
uint8_t ul_ongoing_facch; /* FACCH/H on uplink */
|
||||
|
||||
/* encryption */
|
||||
int ul_encr_algo; /* A5/x encry algo downlink */
|
||||
int dl_encr_algo; /* A5/x encry algo uplink */
|
||||
int ul_encr_key_len;
|
||||
int dl_encr_key_len;
|
||||
uint8_t ul_encr_key[MAX_A5_KEY_LEN];
|
||||
uint8_t dl_encr_key[MAX_A5_KEY_LEN];
|
||||
|
||||
/* measurements */
|
||||
struct {
|
||||
uint8_t clock; /* cyclic clock counter */
|
||||
int8_t rssi[32]; /* last RSSI values */
|
||||
int rssi_count; /* received RSSI values */
|
||||
int rssi_valid_count; /* number of stored value */
|
||||
int rssi_got_burst; /* any burst received so far */
|
||||
float toa_sum; /* sum of TOA values */
|
||||
int toa_num; /* number of TOA value */
|
||||
} meas;
|
||||
|
||||
/* handover */
|
||||
uint8_t ho_rach_detect; /* if rach detection is on */
|
||||
};
|
||||
|
||||
struct l1sched_ts {
|
||||
uint8_t mf_index; /* selected multiframe index */
|
||||
uint32_t mf_last_fn; /* last received frame number */
|
||||
uint8_t mf_period; /* period of multiframe */
|
||||
const struct trx_sched_frame *mf_frames; /* pointer to frame layout */
|
||||
|
||||
struct llist_head dl_prims; /* Queue primitves for TX */
|
||||
|
||||
/* Channel states for all logical channels */
|
||||
struct l1sched_chan_state chan_state[_TRX_CHAN_MAX];
|
||||
};
|
||||
|
||||
struct l1sched_trx {
|
||||
struct gsm_bts_trx *trx;
|
||||
struct l1sched_ts ts[TRX_NR_TS];
|
||||
};
|
||||
|
||||
struct l1sched_ts *l1sched_trx_get_ts(struct l1sched_trx *l1t, uint8_t tn);
|
||||
|
||||
/*! \brief how many frame numbers in advance we should send bursts to PHY */
|
||||
extern uint32_t trx_clock_advance;
|
||||
/*! \brief advance RTS.ind to L2 by that many clocks */
|
||||
|
@ -10,43 +133,43 @@ extern uint32_t transceiver_last_fn;
|
|||
|
||||
|
||||
/*! \brief Initialize the scheudler data structures */
|
||||
int trx_sched_init(struct trx_l1h *l1h);
|
||||
int trx_sched_init(struct l1sched_trx *l1t);
|
||||
|
||||
/*! \brief De-initialize the scheudler data structures */
|
||||
void trx_sched_exit(struct trx_l1h *l1h);
|
||||
void trx_sched_exit(struct l1sched_trx *l1t);
|
||||
|
||||
/*! \brief Handle a PH-DATA.req from L2 down to L1 */
|
||||
int trx_sched_ph_data_req(struct trx_l1h *l1h, struct osmo_phsap_prim *l1sap);
|
||||
int trx_sched_ph_data_req(struct l1sched_trx *l1t, struct osmo_phsap_prim *l1sap);
|
||||
|
||||
/*! \brief Handle a PH-TCH.req from L2 down to L1 */
|
||||
int trx_sched_tch_req(struct trx_l1h *l1h, struct osmo_phsap_prim *l1sap);
|
||||
int trx_sched_tch_req(struct l1sched_trx *l1t, struct osmo_phsap_prim *l1sap);
|
||||
|
||||
/*! \brief PHY informs us of new (current) GSM freme nunmber */
|
||||
int trx_sched_clock(uint32_t fn);
|
||||
|
||||
/*! \brief handle an UL burst received by PHY */
|
||||
int trx_sched_ul_burst(struct trx_l1h *l1h, uint8_t tn, uint32_t fn,
|
||||
int trx_sched_ul_burst(struct l1sched_trx *l1t, uint8_t tn, uint32_t fn,
|
||||
sbit_t *bits, int8_t rssi, float toa);
|
||||
|
||||
/*! \brief set multiframe scheduler to given physical channel config */
|
||||
int trx_sched_set_pchan(struct trx_l1h *l1h, uint8_t tn,
|
||||
int trx_sched_set_pchan(struct l1sched_trx *l1t, uint8_t tn,
|
||||
enum gsm_phys_chan_config pchan);
|
||||
|
||||
/*! \brief set all matching logical channels active/inactive */
|
||||
int trx_sched_set_lchan(struct trx_l1h *l1h, uint8_t chan_nr, uint8_t link_id,
|
||||
int trx_sched_set_lchan(struct l1sched_trx *l1t, uint8_t chan_nr, uint8_t link_id,
|
||||
int active);
|
||||
|
||||
/*! \brief set mode of all matching logical channels to given mode(s) */
|
||||
int trx_sched_set_mode(struct trx_l1h *l1h, uint8_t chan_nr, uint8_t rsl_cmode,
|
||||
int trx_sched_set_mode(struct l1sched_trx *l1t, uint8_t chan_nr, uint8_t rsl_cmode,
|
||||
uint8_t tch_mode, int codecs, uint8_t codec0, uint8_t codec1,
|
||||
uint8_t codec2, uint8_t codec3, uint8_t initial_codec,
|
||||
uint8_t handover);
|
||||
|
||||
/*! \brief set ciphering on given logical channels */
|
||||
int trx_sched_set_cipher(struct trx_l1h *l1h, uint8_t chan_nr, int downlink,
|
||||
int trx_sched_set_cipher(struct l1sched_trx *l1t, uint8_t chan_nr, int downlink,
|
||||
int algo, uint8_t *key, int key_len);
|
||||
|
||||
/* \brief close all logical channels and reset timeslots */
|
||||
void trx_sched_reset(struct trx_l1h *l1h);
|
||||
void trx_sched_reset(struct l1sched_trx *l1t);
|
||||
|
||||
#endif /* TRX_SCHEDULER_H */
|
||||
|
|
|
@ -454,7 +454,7 @@ static int trx_data_read_cb(struct osmo_fd *ofd, unsigned int what)
|
|||
fprintf(stderr, "%s\n", deb);
|
||||
#endif
|
||||
|
||||
trx_sched_ul_burst(l1h, tn, fn, bits, rssi, toa);
|
||||
trx_sched_ul_burst(&l1h->l1s, tn, fn, bits, rssi, toa);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
Loading…
Reference in New Issue