forked from sdr/sdrangelove
DSPEngine: fix FIFO handling
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@ -220,7 +220,7 @@ void DSPEngine::work()
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imbalance(part2begin, part2end);
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// feed data to handlers
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for(SampleSinks::const_iterator it = m_sampleSinks.begin(); it != m_sampleSinks.end(); it++)
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(*it)->feed(part1begin, part1end, firstOfBurst);
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(*it)->feed(part2begin, part2end, firstOfBurst);
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firstOfBurst = false;
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}
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